Macros that are defined under config but not used anywhere.

[Kazu Hirata <kazu at cs dot umass dot edu>]

Hi,

Attached is a list of macros that are defined under config but not
used anywhere.  Feel free to remove these macros if you are a target
maintainer.  Otherwise, I'll probably submit a patch to remove them.

Excuse me for false positives and false negatives.

Kazu Hirata

alpha:
ADA_LONG_TYPE_SIZE
HOST_OBJECT_SUFFIX
STDC_HEADERS

arc:

arm:
ARM_INDEX_REGISTER_RTX_P
FIRST_LO_REGNUM
FL_VFPV2
TARGET_CPU_arm250
TARGET_CPU_arm3
TARGET_CPU_arm600
TARGET_CPU_arm7
TARGET_CPU_arm700
TARGET_CPU_arm7100
TARGET_CPU_arm7500
TARGET_CPU_arm7dm
TARGET_CPU_arm7dmi
TARGET_FPE
TARGET_SOFT_FLOAT_ABI

avr:
XEXP_

c4x:
ASM_OUTPUT_ASM
ASM_PROG
BITS_PER_HIGH
BITS_PER_LO_SUM
EXPENSIVE_CLASS_P
EXT_CLASS_P
IIE_REGNO
IIF_REGNO
IS_INT_OR_PSEUDO_REG
IS_STD_REG
LD_PROG
LEGITIMATE_DISPLACEMENT_P
PACK_INSNS

cris:
CRIS_CANONICAL_MOF_REGNUM
CRIS_GOTPLT_SUFFIX
CRIS_PLT_GOTOFFSET_SUFFIX
FORCE_EH_FRAME_INFO_IN_DATA_SECTION
STDIO_INCLUDED
TARGET_EXPAND_MUL

fr30:
ACCUMULATOR_REGNUM
RETURN_POINTER_MASK

frv:
ASM_OUTPUT_DWARF_ADDR
CR_MASK
CR_NUM
CR_SHIFT_RIGHT
FCC_MASK_E
FCC_MASK_G
FCC_MASK_L
FCC_MASK_U
FIRST_CYCLE_MULTIPASS_SCHEDULING
FIRST_CYCLE_MULTIPASS_SCHEDULING_LOOKAHEAD
GPR_FP
GPR_SP
ICC_MASK_NZ
ICC_MASK_V
ICC_MASK_ZC
MAX_STACK_IMMEDIATE_OFFSET
MD_CALL_PROTOTYPES
MINIMAL_SECOND_JUMP_OPTIMIZATION
RCSP_SOFTWARE_PIPELINING
REGSTATE_UNUSED
TARGET_COND_EXEC
TARGET_FPR_64
TARGET_GPR_64
TARGET_MULTI_CE
TARGET_NESTED_CE
TARGET_VLIW_BRANCH

h8300:

i386:
ASM_OPERAND_LETTER
ASM_OUTPUT_DWARF_ADDR_CONST
AT_SP
BASEADDRESS
DIRFLAG_REG
DLL_IMPORT_EXPORT_PREFIX
FILE_NAME_ABSOLUTE_P
GROUP_BITFIELDS_BY_ALIGN
HOST_PTR_AS_INT
INTEGER_CLASS_P
IS_STACK_MODE
NON_STACK_REG_P
REGNO_OK_FOR_DIREG_P
REGNO_OK_FOR_SIREG_P
REWRITE_ADDRESS
SLOW_SHORT_ACCESS
TARGET_CPU_DEFAULT_athlon
TARGET_CPU_DEFAULT_athlon_sse
TARGET_CPU_DEFAULT_i386
TARGET_CPU_DEFAULT_i486
TARGET_CPU_DEFAULT_k6
TARGET_CPU_DEFAULT_k6_2
TARGET_CPU_DEFAULT_k6_3
TARGET_CPU_DEFAULT_pentium
TARGET_CPU_DEFAULT_pentium2
TARGET_CPU_DEFAULT_pentium3
TARGET_CPU_DEFAULT_pentium4
TARGET_CPU_DEFAULT_pentium_mmx
TARGET_CPU_DEFAULT_pentiumpro
TARGET_MEMORY_MISMATCH_STALL
TARGET_SSE_TYPELESS_LOAD0
TARGET_USE_BIT_TEST
WIN32_UWIN_TARGET

ia64:
REG_GP
UNW_FLAG_MASK
UNW_FLAG_OSMASK
UNW_VER

ip2k:
ASM_OUTPUT_BYTE
ASM_OUTPUT_CHAR
ASM_OUTPUT_DOUBLE
ASM_OUTPUT_FLOAT
ASM_OUTPUT_INT
ASM_OUTPUT_SHORT
C_FLAG
DC_FLAG
FRA_REG
LRA_REG
REG_CALLL
REG_MULH
REG_PCH
REG_PCL
REG_STATUS
REG_ZERO
Z_FLAG

m32r:
ACCUM_P
ASM_ENDIAN_SPEC
CARRY_P
CC1_ENDIAN_SPEC
LINK_ENDIAN_SPEC
LINUX_DEFAULT_ELF
LONG_INSN_SIZE
LOOP_TEST_THRESHOLD
SHORT_INSN_SIZE
TARGET_RELAX_MASK
TARGET_SDATA_SDATA
UINT32_P

m68hc11:
DEFAULT_HARD_FP_REGNUM
FAKE_REG_P
HARD_AP_REGNUM
REGNO_OK_FOR_INDEX_P2
TARGET_M68HC11
TARGET_M68S12
TARGET_OP_TIME

m68k:
EXPXBITS
INT_OP_STANDARD
M68K_CPU_m68010

mcore:
LK_REG
MCORE_STRUCT_ARGS
REG_PUSH_LENGTH
TARGET_MCORE

mips:
BIGGEST_MAX_ARGS_IN_REGISTERS
DFMODE_NAN
PIC_OFFSET_TABLE_MASK
SFMODE_NAN
SINGLE_WORD_MODE_P
TARGET_DEBUG_F_MODE
TARGET_DEBUG_I_MODE
TARGET_MIPS4100
TARGET_MIPS4300
TARGET_MIPS4KC
TARGET_MIPS5KC
TARGET_SB1
TUNE_SB1
TUNE_SR71K

mmix:
FUNCTION_INCOMING_ARG_REGNO_P

mn10300:
CLASS_CANNOT_CHANGE_SIZE
REGNO_AM33_P
REGNO_FP_P

ns32k:
LONG_FP_REGS_P

pa:
INT_32_BITS
OBJ_ELF

pdp11:
CASE_TAKES_INDEX_RAW
COMPARE_FLAG_MODE
TARGET_10
TARGET_NO_AC0
TARGET_NOSPLIT

rs6000:
ALWAYS_PUSH_CONSTS_USING_REGS_P
FASCIST_ASSEMBLER
RS6000_SAVE_TOC
TARGET_MACOS
TARGET_NO_EABI

s390:
ADDR_REG_P
FRAME_REG_P
TARGET_CPU_IEEE_FLOAT

sh:
PIC_REFERENCE_P
SH_DWARF_FRAME_BT0
SH_DWARF_FRAME_PR_MEDIA

sparc:
ASM_FLOAT
ASM_INT_OP
ASM_LONGDOUBLE
BASE_PASSING_ARG_REG
TARGET_CPU_sparc64
TARGET_CPU_sparc86x
TARGET_CPU_sparcv9
TARGET_CPU_v7
TARGET_IMPURE_TEXT

stormy16:

v850:
ENABLE_REGMOVE_PASS
INT_7_BITS
REG_OK_FOR_BASE_P_STRICT
REG_OK_FOR_INDEX_P_STRICT

vax:
VMS_TARGET

xtensa:
DWARF_UNWIND_INFO
LIBCALL_OUTGOING_VALUE

i860:
LITERAL_COMPARE_BETTER_UNSIGNED
SMALL_INTVAL
TARGET_XP

iq2000:
BRANCH_LIKELY_P
CLASS_CANNOT_CHANGE_MODE
CLASS_CANNOT_CHANGE_MODE_P