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Re: Pre_dec and Post_inc insns
- From: Hans-Peter Nilsson <hp at bitrange dot com>
- To: tm_gccmail at mail dot kloo dot net
- Cc: Natasha Wilson <nat_w at operamail dot com>, <gcc at gcc dot gnu dot org>
- Date: Wed, 9 Jul 2003 00:37:51 -0400 (EDT)
- Subject: Re: Pre_dec and Post_inc insns
On Tue, 8 Jul 2003 tm_gccmail@mail.kloo.net wrote:
> IMHO, the pre/post dec/inc shouldn't be generated before sched1 because
> these cause major problems with instruction scheduling.
>
> Consider a processor with a memory load latency of two clocks:
>
> mov.l @r4+,r1
> mov.l @r4+,r2
> mov.l @r4+,r3
> add r2,r3
>
> sched1 will be unable to reorder this sequence to:
>
> add #4,r4
> mov.l @r4+,r2
> mov.l @r4,r3
> add #-8,r4
> mov.l @r4,r1
> add r2,r3
>
> because of the post-increment addressing.
But if the load latency is one insn, then reordering would not
be a certain win, and might instead lose, at least size-wise.
> IMHO, the pre/post increment/decrement addressing modes should be
> generated after sched1 to give the first scheduling pass maximum freedom
> for reordering instructions.
IMHO whether to have autoincdec at sched1 should be
target-dependent, supposedly through an option like others set
by a target at OPTIMIZE_OPTIONS, after careful measurements.
brgds, H-P