This is the mail archive of the gcc@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: Compiler optimization?


Joe Buck wrote:
On Tue, Jun 10, 2003 at 05:41:13PM -0700, Chirag Wighe wrote:
I am an embedded developer and I am trying to understand the endian issues with respect to compilers and how they access structure fields.

Is it possible for an optimizing compiler to combine the two half word writes into a single word write.

Gcc isn't very good about optimizing stores, but it will optimize the loads. If you load one of the shorts, gcc will load an int instead. If you load both of the shorts near each other, one of the int loads will be optimized away. (This is assuming a 32-bit target.) This will fail in your case. You can prevent that by using volatile as Joe Buck mentioned.


Obviously the 32-bit constant that would be stored depends on the
endian-ness of the target.

Some systems allow one to specify data endianness separately from cpu endianness. I think this is what he is referring to. This can be useful when moving data between two systems with different cpu-endianness. Gcc doesn't directly support this. There have been occasional requests for an endianness attribute for data, but I am not convinced that it is a good idea.


See for instance the IA-64 assembler which has .lsb and .msb directives which specify endianness of the current section only. This allows you to assemble a file that has both big and little endian data.

Jim


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]