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Re: Optimizing for Low Power Consumption
On Tue, 3 Jun 2003, Peter Barada wrote:
> > Before anyone can even try to scope this, it would help immeasurably
> > to provide some examples of what's a high-power instruction sequence, and
> > then its equivalent low-power instruction sequence. Then we might be
> > able to suggest an approach you could use. The more sequences you
> > provide, the better we can make suggestions.
On Tue, Jun 03, 2003 at 06:06:54PM -0400, Christopher Wolff wrote:
> For instance, the instruction
>
> ADDD m ; add to 16-bit register D
>
> will be more expensive than using the two instructions
>
> ADDB m+1 ; accumulators A & B are the high and low order bytes of D
> ADCA m ; add with carry
The general rule for any processor is that it costs more energy to drive
signals off-chip, or even a long distance on the same chip; in particular,
memory reads are expensive. Just bumping up penalties for going to memory
might help a good deal.
> Also, on the average, instructions using the B accumulator will consume
> less power than the A accumulator, except in Indexed X addessing mode.
Now *that* is something that I wouldn't have predicted.