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Address Arithmetic Improvement
- From: "Rakesh Kumar - Software, Noida" <rakeshku at noida dot hcltech dot com>
- To: gcc at gcc dot gnu dot org
- Cc: Alexandre Oliva <aoliva at redhat dot com>, Jan Hubicka <jh at suse dot cz>
- Date: Wed, 9 Apr 2003 17:27:40 +0530
- Subject: Address Arithmetic Improvement
Processor: SH4
Mode: Little Endian
On compiling the attached program with -O2, I observed that
reload pass splits up the DF mode address arithmetic insn
into SF mode insns using FPSCR register.
I believe SH4 has the restriction that in little endian, we
can't use double-precision floating-point moves between
memory and registers.
But generating two insns, where one would suffice, encourage
redundancy. Also to adjust the pointers, we are generating
additional insns as defined in define_split in sh.md.
I propose that one function could be developed which scans the
basic block and combines address arithmetic insns. But I'm
not clear about where to put it so that it should not affect the present compilation process.
Can anybody there suggest me some alternative?
Thanks in
advance
Rakesh
Kumar
Attachment:
address.c
Description: Binary data