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Re: Status of SSE builtins
> Jan Hubicka wrote:
> >
> > > Jan Hubicka wrote:
> > > > Not yet, however I think this is just part of the problem, as reload
> > > > will offload the register to memory, read it back and clobber the upper
> > > > part. I will check
> > >
> > > You'll have to define reload patterns that copy the SSE register into the
> > > GP register first, than load the value into the desired subreg of the GPR,
> > Moving SSE into GP is kind of overkill. You need 4 registers on 5
> > GPR register machine ;(.
>
> We are interested in a working compiler first. And it's a 5 GPR
> register machine only when compiling -fpic -fno-omit-frame-pointer.
> Of course, you can try to get thius stuff through secondary memory, although
> I'm not sure that this will work unless you load memory by using a reload through
> GPR and a secondary reload through memory.
> Or if you reserve a few bytes just in case, or fiddle with machine_dependent_reorg ;-)
>
> > Loading two SSE registers into GPR is already
> > impossible.
>
> You don't need to. Just manipulate the SSE register with the word you want
> to change.
Reload definitly reloads whole register. I already run into this problem on
instruction dealing with (subreg:SI (reg:DF)). In this case reload
decided to reload whole subreg into integer registers (killing 4
registers) and reload the subreg (SImode register) into yet another
register (killing another 2) crashing on PIC.
I've fixed it to do this excercise only for output reload that saves 2
registers and makes us to fit, but for SSE this won't work.
I will try to figure out how to deal with this. At the moment we even
can't store vector modes in integer registers (even when it is possible)
Honza
>
> > Honza
> > > then write back to the SSE register.
> > >
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>
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> --------------------------
> SuperH (UK) Ltd.
> 2410 Aztec West / Almondsbury / BRISTOL / BS32 4QX
> T:+44 1454 465658