Re: [DFA]: Scheduling for zSeries and S/390

[Vladimir Makarov <vmakarov at redhat dot com>]

Hartmut Penner wrote:
> 
> Vlad wrote:
> 
> >  I'd name your variant of description as a structural one because it is
> >close to processor documentation. You could also use what I name a
> >behavioural description.  Such description does not follow processor
> >description but correctly describes all pipeline hazards.  For example,
> >you could remove dec, agen, c1, and c2 and still get the same
> >automaton.  Usage of structural or behavioral description is a matter of
> >taste.
> 
> I guess, I'll change it to behavioral description.
> 
> One more question I have, how could I model the behavior of the
> Load address instruction, which has a special bypass to agen.
> 
> The behavior is as follow:
> 
> cycle   0     1      2      3      4      5      6      7
>        LA     .      L
>        LA     x      .      L
>        LA     x      x      .      L
>        LA     x      x      x      .      L
>        LA     x      x      x      x      L
> 
> where LA sets address register used in L, . is a pipeline stall and x is
> any unrelated instruction.
> That means, the LA is a 2 cycle instruction only in case of less than 4
> instruction between, 1 cycle
> in all other cases.

  I don't think it should (or can) described by DFA.  Although we still
need to describe such processor feature.  It becomes more common.  Fore
example, Itanium 1 MM-insn latency time is for 4 cycle if there is at
least 4 cycles between producer and consumer insns and 10 cycles
otherwise.

  The insn scheduler should have adequate solution to this problem.  Now
you can only reorder ready queue (through hooks to improve insn
scheduling).  This reorder should place L insn at the end of ready queue
until more 4 cycles have gone after issue of the corresponding LA insn.

  I'll try to implement a common mechanism for insn scheduler and
construction (like bypass) for descriptions of such insn.  I can not
promise only when it will be in the main line.

Vlad