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A new branch has been created.


  Hello, I've created a branch (itanium-sched-branch).  The
branch will be used for improving insn scheduling for Itanium
processors (currently only for original Itanium processor).  The work
will be based on the DFA insn scheduler.

  The major goal is to speed up the compiler without worsening code
quality.  The big part of compilation time for Itanium now is spent in
insn scheduler.  Gcc now loses in comparisons with other compilers for
Itanium.  For example, Intel compiler is much faster (up to 2 times)
and generates a better code.  It is difficult to improve code
quality without rewriting insn scheduler because currently gcc has a
very good manual tuning of insn scheduler for Itanium. Therefore the
major goal is to bring gcc compilation speed closer to Intel
compiler's one for Itanium processors.

  As I side effect of the work, I expect simplification of ia64.c code
concerning insn scheduling tuning and creation a base for easier insn
scheduler tuning for Itanium2 when the time comes.

  I am planning to commit the following patches into the branch during
a next few weeks.

  1. DFA based pipeline hazard recognizer generator (genautomata.c)
     patches for better description of Itanium processors.

  2. Insn scheduler patches for better tuning it for Itanium.

  3. Machine depended patches (ia64.c and ia64.md) to generate bundle
     templates using DFA based description.

  If the major goal is achieved, we could merge the branch into the
main line.

Vlad


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