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Re: -msse producing sse2 instructions
> On Sunday 21 July 2002 06:28, Andreas Jaeger wrote:
> > "Dylan Cuthbert" <dylan@q-games.com> writes:
> ....
> > > I'm compiling currently
> > > with -mfpmath=387 -msse -mcpu=pentium3 -march=pentium3 and gcc 3.1.1-4
> > > from the very latest experimental cygwin distribution.
> > >
> > >
> > > One of the problems with tracking this down is my machine is an Athlon MP
> > > and has no trouble with SSE2 instructions, however a client's machine is
> > > an Athlon 4 and exhibits the problem. And of course we need the SSE
> > > builtins for speed improvements. -_-;;
> >
> > Athlon 4s do not have SSE2, they're the same as Athlon MP (both have
> > SSE only).
> >
> > Btw. cvttss2si is an SSE instruction, not an SSE2 one AFAIK.
> > Therefore are you sure that you get an Illegal instruction for
> > cvttss2si? Or is this some other error and you're just confused.
> >
> > Andreas
> -march=pentium3 doesn't set x86_partial_reg_dependency as =athlon and
> =pentium4 do. This is the flag which tells gcc to use movaps for register to
> register moves. This sometimes causes sse code to be slower than 387 code.
> If it were not for this problem, -march=pentium3 would be a good common
> denominator for P3/P4/AthlonMP.
>
I have patch for this problem. I will commit it soon.
> The cvttss2si instructions are working fine on my old P-III's.
Perhaps the chip has SSE disabled by bios or the Windows you are using
is not SSE aware?
Honza
>
> How are you dealing with alignment with your cygwin binutils? You would not
> be able to use sse parallel memory instructions without applying 16-byte
> alignment. At least, the odds are against them. I think Chris Faylor
> decided to stay with 4-byte alignment for backwards compatibility with the
> libstdc++-v2 libraries.
> --
> Tim Prince