This is the mail archive of the
gcc@gcc.gnu.org
mailing list for the GCC project.
Re: Sharing hard registers
- From: Jan Hubicka <jh at suse dot cz>
- To: Alan Lehotsky <apl at alum dot mit dot edu>
- Cc: law at redhat dot com, Eric Christopher <echristo at redhat dot com>,gcc at gcc dot gnu dot org, gcc-patches at gcc dot gnu dot org
- Date: Fri, 14 Jun 2002 11:59:16 +0200
- Subject: Re: Sharing hard registers
- References: <2387.1024007246@porcupine.cygnus.com> <a05111a12b92efbc4965c@[63.214.71.88]>
> At 4:27 PM -0600 6/13/02, law@redhat.com wrote:
> >In message <200206132203.g5DM3lv24315@potter.sfbay.redhat.com>,
> >"Eric Christoph
> >er" writes:
> > > On Thu, 13 Jun 2002 13:27:39 -0700, law wrote:
> > >
> > >
> > > > It may be necessary to back out the last patch which makes gen_rtx_REG
> > > > share hard registers in some circumstances.
> > > >
>
> The porting guide's "Structure Sharing Assumptions" needs to
> be updated to
> explicitly indicate that hard registers are "shared". Right
> now, it just says
> that pseudos are always shared.
Pseudo registers are always shared. We are speaking abou hard registers
here and I believe it has been always documented in a way that they can
be shared or not. At least that way gcc worked for a while.
Honza
>
> Also, I'm curious about the issue of a hard-register with
> more than one mode.
> How does that work if R1 can be a SF or a SI mode value???
>
> Doesn't the mode get in the way of sharing the hard register?
> Or is this cached
> by (mode,regno).?
>
> --
> Quality Software Management
> http://home.earthlink.net/~qsmgmt
> apl@alum.mit.edu
> (978)287-0435 Voice
> (978)808-6836 Cell
>
> Software Process Improvement / Management Consulting
> Language Design / Compiler Implementation