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Re: Big-endian Gcc on Intel IA32
- From: dewar at gnat dot com
- To: dewar at gnat dot com, fw at deneb dot enyo dot de
- Cc: gcc at gcc dot gnu dot org, torvalds at transmeta dot com
- Date: Sun, 23 Dec 2001 09:59:54 -0500 (EST)
- Subject: Re: Big-endian Gcc on Intel IA32
<<I wouldn't tackle this problem at the struct level, but at the
discrete type level, IOW introduce additional integer types with
different resentation. This would already greatly help in many cases.
>>
Yes, I already suggested this, and noted that this was what we did
in Realia COBOL (see archives)
<<If you've got signed-magnitude representation, you've got plenty of
positions in which you can place the sign bit.
>>
There are no S&M machines, so this is bogus. There are 1's complement machines
but the issue is not affected by 1s or 2s complement. Even for S&M, the
sign bit was always the most significant, so you are inventing a non-existant
problem here.
<<If the machine is word-adressed, all we do in this regard won't help
much to increase portability because a lot of data structures with a
given external representation assume you can access individual octets,
and the mapping to a useful machine implementation is certainly not
straightforward. For example, how does an IP header look on a 36 bit
machine?
>>>
The point is that it is quite straightforward to address the problem WITHIN
an address unit. Ada already does this. Have a look at what GNAT implements
here with the Bit_Order attribute (and also see the discussion of why it
is not easy to do more). This is in the GNAT RM.