Re: powerpc & unaligned block moves with fp registers

[David Edelsohn <dje at watson dot ibm dot com>]

>>>>> DJ Delorie writes:

>> > Sigh.  DJ wants 3, not 2.  That's what PPC chips support in hardware,
>> > right?
>> 
>> Not quite; as David pointed you will get an exception if the fetch
>> crosses a page boundary.  Most of the time you won't.

DJ> Oh, right.  Makes sense to me now.  Thanks!

	The PowerPC Book I says that an alignment exception only occurs if
an FP load or store is not word-aligned.  I am pretty sure that my
research OS sometimes hit an exception beyond just a page fault, but maybe
it was not an alignment exception.  If the only concern is alignment
traps, maybe word-alignment (as currently defined by
SLOW_UNALIGNED_ACCESS) is sufficient. 

	If you want to be really safe, you should redefine
SLOW_UNALIGNED_ACCESS for your target so that it only accepts natural
alignment and any processor-specific requirements.  If word-alignment is
sufficient, you can use the default SLOW_UNALIGNED_ACCESS definition.

	It sounds like Zack's customer needs SLOW_UNALIGNED_ACCESS true
for DImode of any alignment.

	Modifying rs6000_emit_move would seem to catch all occurances, as
Dale pointed out, and be the least intrusive.

Thanks, David