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WORD_REGISTER_OPERATIONS/LOAD_EXTEND_OP
- To: <gcc at gcc dot gnu dot org>
- Subject: WORD_REGISTER_OPERATIONS/LOAD_EXTEND_OP
- From: Bernd Schmidt <bernds at redhat dot com>
- Date: Fri, 6 Apr 2001 17:22:15 +0100 (BST)
Can someone tell me what assumptions are made by this piece of code in
combine.c (nonzero_bits):
#if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
/* If this is a typical RISC machine, we only have to worry
about the way loads are extended. */
if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
? (((nonzero
& (((unsigned HOST_WIDE_INT) 1
<< (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
!= 0))
: LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
#endif
I've got a sparc testcase here (PR 1061) where a masking operation is missing
in the output. It appears that this piece of code assumes that if W_R_O and
L_E_O are defined, an expression like (subreg:SI (reg:HI x)) always has all
bits zero in the upper half. This isn't the case, though - this seems like
it's just an invalid optimization and should be removed.
Comments?
Bernd