Re: cross gcc port problem

[Hans-Peter Nilsson <hans-peter dot nilsson at axis dot com>]

> Date: Sun, 18 Mar 2001 22:00:25 -0500
> From: Alan Lehotsky <apl@alum.mit.edu>

> >>     And the second problem is the absence of the "compare" instructions in
> >> this processor. So I've defined this operation with substraction
> >> instructions, but as side effect my compare instruction alters the
> >> accumulator register, so I've tried to write something like:
> >> (define_insn "cmpqi"
> >>   [(set (cc0)
> >>         (compare (match_operand:QI 0 "register_operand" "r")
> >>                  (match_operand:QI 1 "general_operand" "m")))
> >>    (clobber (reg:QI 0))]
> >>     but again has no luck. :-(( Because gcc "performs" this insn in parallel
> >> and the only valid operand also comes in reg:QI 0, gcc aborts. So, can
> >> anyone advise me how to specify clobbering correctly?
> >
> >Try having a "define_expand" for this.
> 
> 	No.  That won't work, because  you CAN'T have any instructions between the CC setter
> 	and the CC consumer or the compiler will crash.

Do you imply that having a clobber on a cmpX expander
necessarily leads to instructions coming between CC0 setter and
user?  I don't see why that is a must.  But IIRC, a cc0-setter
must be a "single-setter"; not a parallel, so I guess a
define_expand to a parallel with a clobber is not a solution
anyway.

> 	I think that you are doomed!  Although if you switched to using CCmode PSEUDOS instead, then I
> 	think that you can have instructions between the "set" of the condition codes and the conditional
> 	jump or other user of the condition codes.

Not necessarily.  The cbranch & Co. patterns would do fine, I
think.

> > Alternatively, you might
> >want to look into defining the "cbranchsi4" and "cmov" patterns.
> >Though I think only the thumb-within-arm target uses it, and it's
> >unfortunately not documented.  See also
> ><URL:http://gcc.gnu.org/ml/gcc/2001-01/msg01806.html> with follow-ups.

brgds, H-P