Re: Number of registers on x86

[dewar at gnat dot com]

<<No. The Pentium does not.

The Pentium is an in-order superscalar (dual-issue) implementation of the
IA32 architecture.
>>

Yes, sorry, my confusion, I was reading Pentium here as generic (and that
was a silly mistake, since you specifically mentioned the P2 and P3). The
true Pentium is sort of an out-of-mind-consigned-to-history chip at this
stage for me :-)

What I meant by saying that RR and OOOE are not necessarily linked is that
RR can still buy you multiple issue possibilities even without OOOE.
Consider

    mov eax, a
    mov b, eax
    mov eax, c
    mov d, eax

(using Intel right to left syntax, destination on left)

If you rename the second eax, then the second and third mov instructions
can be dual issued, without any out of order execution.

Yes, most certainly I agree that renaming increases the opportunities
for OOOE, in this particular case, the 1st and 3rd moves can be dual
issued, with the 3rd mov thus being issued before the 2nd.

Note that on an EPIC architecture, or indeed a more conventional VLIW
archictecture, where, by definition there is no out of order execution
(that's the whole point of these kind of architectures, that issue is
controlled by the compiler, not the hardware), renaming could still
buy you something by increasing the opportunities for multiple issue.