Re: leave instruction on ppro/pII/pIII

[Alexander Sokolov <robocop at netlink dot ru>]

On Wed, 10 May 2000, Jeffrey A Law wrote:

> 
>   In message <Pine.LNX.4.10.10005101428240.12070-100000@ns.netlink.ru>you write
> :
>   > It seems that gcc uses leave instruction only when generating code for
>   > 386, amd k6 and athlon processors. On all others it uses an equivalent
>   > movl %ebp,%esp popl %ebp sequence. I think that using leave on ppro, pII
>   > and pIII could be advantageous for the following two reasons:
>   > 
>   > 1. Both leave and movl/popl are broken down to the same 3 micro-ops,
>   > but leave is only one byte instruction, whereas a sequence of movl/popl
>   > takes 3 bytes.
> True, but in an out of order execution machine, you're better off generating
> the simpler instructions as they can issue/retire interleaved with other
> non-epilogue instructions.
>
> It probably does make sense to use "leave" when optimizing for size though
> and a patch to do this would be appreciated.  I'm much less sure about
> using "leave" when not optimizing for size on ppro, PII & PIII.

Since decoders issue micro-ops in-order and retirement unit retires them
in-order, if there are no instructions generated between "movl %ebp,%esp"
and "popl %ebp" then if we change this sequence to "leave" we get exactly
the same 3 micro-ops issued by decoders which have to retire in exactly
the same order.


-- 
Alexander Sokolov
System Administrator
Netlink Co. Ltd., Moscow
Tel/Fax: +7 095 2786139