Re: Enabling SSA for alpha?

[Jeffrey A Law <law at cygnus dot com>]

  In message <200003151821.NAA25480@polya.math.purdue.edu>you write:
  > The alpha 21264 has the following constraint on floating-point
  > ops in IEEE arithmetic: The destination register must not be
  > the same as either of the source registers.  Gcc's register
  > allocator does not deal well with this constraint, and generally
  > generates a lot of fmov's to satisfy it.  Since it is claimed
  > that the 21364 will use the 21264 CPU core, this problem will
  > not go away soon.
  > 
  > If gcc transformed floating-point code to SSA form, then
  > the register allocator should do a much better job of assigning
  > registers to pseudo-registers for floating-point code, since there
  > will be no overlap at all of source and destination pseudo-registers.
  > 
  > So, my question:  How (and where) do I enable the SSA transformation
  > in gcc to see if, in fact, it does improve the register allocation
  > significantly?
SSA is not suitable for direct code generation -- you translate into SSA,
perform a series of transformations (optimizations), then translate back
out of SSA.

Some of the transformations you can do with SSA can help register allocation,
then again, some can hurt if you are not careful.

You also have to be careful not to run afoul of patents when working inside
the register allocator.



jeff