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Re: bug handling instructions with multiple delay slots
- To: Alan Lehotsky <lehotsky at tiac dot net>
- Subject: Re: bug handling instructions with multiple delay slots
- From: Jeffrey A Law <law at cygnus dot com>
- Date: Fri, 05 Nov 1999 00:09:36 -0700
- cc: gcc at gcc dot gnu dot org, m dot hayes at elec dot canterbury dot ac dot nz (Michael Hayes)
- Reply-To: law at cygnus dot com
In message <v04220807b4475f1fe483@[192.168.1.254]>you write:
> 1/ if a DEFINE_DELAY describes an instruction with TWO dissimilar
> delay slots, we don't correctly handle validating the instruction
> that ends up in the N-th delay slot against the "condition" for
> that particular slot.
>
> 2/ I have a case where the first of two delay slots gets a CC0 setter
> and the second gets something that will clobber those condition
> codes. [The setter comes from the branch-target, while the instruction
> that clobbers comes from the fall thru]
I believe both of these were fixed some time ago.
jeff