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bug handling instructions with multiple delay slots
- To: gcc at gcc dot gnu dot org
- Subject: bug handling instructions with multiple delay slots
- From: Alan Lehotsky <lehotsky at tiac dot net>
- Date: Thu, 4 Nov 1999 11:11:55 -0500
- Cc: m dot hayes at elec dot canterbury dot ac dot nz (Michael Hayes)
I'm still back on 2.8.1 (with some of egcs 1.1.2), and see the following
problems with reorg.
1/ if a DEFINE_DELAY describes an instruction with TWO dissimilar
delay slots, we don't correctly handle validating the instruction
that ends up in the N-th delay slot against the "condition" for
that particular slot.
2/ I have a case where the first of two delay slots gets a CC0 setter
and the second gets something that will clobber those condition
codes. [The setter comes from the branch-target, while the instruction
that clobbers comes from the fall thru]
I believe that the second problem violates the axiom that the CC0 setter
and CC0 user are required to be adjacent instructions. [I also suspect
that I have another bug in that I don't abort() detecting this in my
define_insn pattern for conditional branches...]
Before I go off and figure out how to fix these, I'm curious if
anyone else with a N-instruction delay slots has already fixed this
and not submitted the patches yet.
I am aware of the C4X code, and have most of their changes (and they
have some of mine, I think)
Regards,
Al Lehotsky
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