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Re: DG/UX Intel Build problem
- To: ehr at listworks dot com
- Subject: Re: DG/UX Intel Build problem
- From: Jeffrey A Law <law at upchuck dot cygnus dot com>
- Date: Tue, 04 May 1999 00:40:18 -0600
- cc: egcs at egcs dot cygnus dot com
- Reply-To: law at cygnus dot com
In message <06fd01be9573$1e3a0890$65c8c8c8@ehrpc.listworks.com>you write:
> 8048e0c: 8d 50 04 leal 0x4(%eax),%edx | 8048e0c:
> 83 05
> 34 89 05 08 04 addl $0x4,0x8058934
This indicates a real problem. The stage1 and stage2 compiled gcc differently.
Note how one used leal and the other addl. Also note how one has a register
destination and the other has a memory destination.
The next step is to start exploring why the stage1 and stage2 compilers
generated different code for this function.
jeff