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Correct RTL representation of reg-stack registers



Hi
Here are my ideas about correct rtl representation.
I think only correct way to represent the "pop" and "push" operations
are parallels with moves like:

(parallel [(set (reg st(0)) (reg st(1)))
(set (reg st(1)) (reg st(2)))
(set (reg st(2)) (reg st(3)))
(clobber (st(3)))])

the number of set insns depends on top of stack position.
I think I can easily write patterns in i386.md to match such insns
using match_parallel (it allows me to use predicate where I can put the
actual checking).

Normal instructions that have popping/nonpopping version will have two patterns
one with parallel representing push operation and one normal.
(I can write predecates like math_push and match_pop to check this)

Some instruction have only popping version (fstp for long double) I believe
will have only normal insn pattern.

Also some comparsion allows one or two pops, so this can be easily handled
by parallel of comparsion and popping insn chain.

Then reg-stack can work bit like a combiner. It will count number of pop
operations it wants to do and try match one with most pops, then one with
fewer pops and finish by matching one with push.

The problem of this solution will be probably large represenation of
the insns (ons insn can be parallel of up to 8 moves). If you have better
idea, let me know.

I would also like to make constraints working for reg-stack correctly.
For example add pattern have multiple versions
(it can do st(0)=st(0)+st(x), st(x)=st(0)+st(x) and some other forms I believe)
so this can be represented in reg-stack by constraints. Reg-stack will then use
reload-like matching algorithm...
"t,f" "0,t" "f,0"
But I am not sure how this will interfere with reload. Maybe we can make some
way to put reload and reg-stack constraints separately.
(the "t" and "f" constraints can be both defined for reload as "any fp register")

I will try to study this topic bit more. I am especially interested in your
toughts about the pop/push part.


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