[980129] Option X => Option Y

[jerry at cs dot ucsb dot edu (Jeremiah W. James)]

This message arises from an effort to make gcc produce n32/mips3 and
64/mips3 libs instead of the default n32/mips3 and 64/mips4 libs.
Those, like me, with mips3 machines would like the library support for
the 64-bit ABI.  Below is a patch that solves the problem, by making
-mabi=64 default to -mips3 instead of -mips4.  I updated the docs a
little, but certainly not enough.

The reason I gave this message its subject line is that I introduced a
bunch of cruft in the patch that could be avoided with one feature.
That is the ability for the initial command-line flag processor to do
this:

   The presence of option X and the absence of option Y means that we
   should pretend the user gave us option f(X,Y).

In this case, that would mean that -mabi=64 and no -mips* option means
"pretend the user gave us -mips3".  If -mips3 is given and no -mabi*
option is given, then "pretend the user gave us -mabi=n32".  This would
do away with the need for most of the following patch.  The cruft came
from repeatedly testing for this kind of situation, and coping with it.

--- iris6.h.orig        Fri Jan  2 14:50:23 1998
+++ iris6.h     Sat Jan 31 15:39:05 1998
@@ -530,11 +530,11 @@
      %{!mabi*:%{mips4:/usr/lib32/mips4/crtn.o%s}\
        %{!mips4:/usr/lib32/mips3/crtn.o%s}}}"
 
-/* ??? If no mabi=X option give, but a mipsX option is, then should depend
-   on the mipsX option.  */
 #undef LINK_SPEC
 #define LINK_SPEC "\
-%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
+%{G*} %{EB} %{EL} \
+%{mips1:%{!mabi*:-32} -mips1} %{mips2:{!mabi*:-32} -mips2} \
+%{mips3:%{!mabi*:-n32} -mips3} %{mips4:{!mabi*:-64} -mips4} \
 %{bestGnum} %{shared} %{non_shared} \
 %{call_shared} %{no_archive} %{exact_version} %{w} \
 %{static: -non_shared} \
@@ -542,4 +542,4 @@
   %{!shared: %{!non_shared: %{!call_shared: -call_shared -no_unresolved}}}} \
 %{rpath} -init __do_global_ctors -fini __do_global_dtors \
 %{shared:-hidden_symbol __do_global_ctors,__do_global_dtors,__EH_FRAME_BEGIN__,__frame_dummy} \
--_SYSTYPE_SVR4 %{mabi=32: -32}%{mabi=n32: -n32}%{mabi=64: -64} %{!mabi*: -n32}"
+-_SYSTYPE_SVR4 %{mabi=32:-32}%{mabi=n32:-n32 %{!mips*:-mips3}}}%{mabi=64:-64 %{!mips*:-mips3}}%{!mabi*:-n32 %{!mips*:-mips3}}"
--- gcc/config/mips/mips.c.orig Tue Jan 27 09:22:43 1998
+++ gcc/config/mips/mips.c      Fri Jan 30 12:03:16 1998
@@ -4033,10 +4033,8 @@
     {
       if (mips_abi == ABI_32)
        mips_isa = 1;
-      else if (mips_abi == ABI_N32)
-       mips_isa = 3;
       else
-       mips_isa = 4;
+       mips_isa = 3;
     }
   /* If both ABI and ISA were specified, check for conflicts.  */
   else if (mips_isa_string && mips_abi_string)
--- mips.h.orig Wed Jan 14 12:57:49 1998
+++ mips.h      Sat Jan 31 16:27:20 1998
@@ -779,7 +779,8 @@
 %(subtarget_asm_optimizing_spec) \
 %(subtarget_asm_debugging_spec) \
 %{membedded-pic} \
-%{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
+%{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32 %{!mips*:-mips3}}\
+%{mabi=64:-64 %{!mips*:-mips3}}%{mabi=n64:-64 %{!mips*:-mips3}} \
 %(target_asm_spec) \
 %(subtarget_asm_spec)"
 
@@ -846,13 +847,16 @@
 #ifndef CC1_SPEC
 #define CC1_SPEC "\
 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
-%{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
-%{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
-%{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
+%{mips1:-mfp32 -mgp32 %{!mabi*:-mabi=32}} \
+%{mips2:-mfp32 -mgp32 %{!mabi*:-mabi=32}} \
+%{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64 %{!mabi*:-mabi=n32}} \
+%{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64 %{!mabi*:-mabi=64}} \
 %{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
 %{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
 %{m4650:-mcpu=r4650} \
 %{m3900:-mips1 -mcpu=r3900 -mfp32 -mgp32} \
+%{mabi=n32:%{!mips*:%{!msingle-float:%{!m4650:-mfp64}} -mgp64 -mips3}} \
+%{mabi=64:%{!mips*:%{!msingle-float:%{!m4650:-mfp64}} -mgp64 -mips3}} \
 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
 %{pic-none:   -mno-half-pic} \
 %{pic-lib:    -mhalf-pic} \
--- gcc/invoke.texi.orig        Mon Jan 26 14:59:50 1998
+++ gcc/invoke.texi     Fri Jan 30 12:53:32 1998
@@ -4351,12 +4351,14 @@
 @table @code
 @item -mcpu=@var{cpu type}
 Assume the defaults for the machine type @var{cpu type} when scheduling
-instructions.  The choices for @var{cpu type} are @samp{r2000}, @samp{r3000},
-@samp{r4000}, @samp{r4400}, @samp{r4600}, and @samp{r6000}.  While picking a
-specific @var{cpu type} will schedule things appropriately for that
-particular chip, the compiler will not generate any code that does not
-meet level 1 of the MIPS ISA (instruction set architecture) without
-the @samp{-mips2} or @samp{-mips3} switches being used.
+instructions.  The choices for @var{cpu type} are @samp{r2000},
+@samp{r3000}, @samp{3900}, @samp{r4000}, @samp{r4100}, @samp{r4300},
+@samp{r4400}, @samp{r4600}, @samp{r4650}, @samp{r5000}, @samp{r6000},
+and @samp{r8000}.  While picking a specific @var{cpu type} will schedule
+things appropriately for that particular chip, the compiler will not
+generate any code that does not meet level 1 of the MIPS ISA
+(instruction set architecture) without the @samp{-mips2}, @samp{-mips3},
+or @samp{-mips4} switches being used.
 
 @item -mips1
 Issue instructions from level 1 of the MIPS ISA.  This is the default.
@@ -4370,7 +4372,11 @@
 @item -mips3
 Issue instructions from level 3 of the MIPS ISA (64 bit instructions).
 @samp{r4000} is the default @var{cpu type} at this ISA level.
-This option does not change the sizes of any of the C data types.
+
+@item -mips4
+Issue instructions from level 4 of the MIPS ISA (conditional move,
+prefetch, enhanced FPU instructions).  @samp{r8000} is the default
+@var{cpu type} at this ISA level.
 
 @item -mfp32
 Assume that 32 32-bit floating point registers are available.  This is