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Re: giv combination patch mark 2
On Sun, Dec 14, 1997 at 08:11:40PM +0100, Toon Moene wrote:
> 0x34ca <gen_insn+478>: movel d2,d0
> 0x34cc <gen_insn+480>: lsll #2,d0
> 0x34ce <gen_insn+482>: movel 0(a2)[d0.l],-232002756(a0)
> 0x34d8 <gen_insn+492>: movel 0(a1)[d0.l],a0@+
> 0x34dc <gen_insn+496>: addql #1,d2
> 0x34de <gen_insn+498>: cmpl d2,d1
> 0x34e0 <gen_insn+500>: bgt 0x34ca <gen_insn+478>
>
> Note the use of a0 in the third and fourth line - it's extremely
> unlikely that *both* addresses are correct, as they are 230 Mbyte
> apart ! Also note that -232002756(a0) is only a valid address using
> my "m680x0 has 32-bit offsets for x >= 2" patch.
Do you have a pointer to that patch handy? Here I get
move.l (%a2,%d0.l),12(%a0)
move.l (%a1,%d0.l),(%a0)+
Of course, the GIVs those came from were
Insn 432: dest address src reg 29 benefit 9 used 1 lifetime 1 replaceable mult 4
add (plus:SI (reg/v:SI 30)
(const_int 60))
Insn 442: dest address src reg 29 benefit 9 used 1 lifetime 1 replaceable mult 4
add (plus:SI (reg/v:SI 30)
(const_int 48))
giv at 442 reduced to (reg:SI 112)
giv at 432 reduced to (plus:SI (reg:SI 112)
(const_int 12))
So I don't immediately see what effect a 32-bit offset could have...
r~