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Re: An alpha egcs bug
- To: rth at cygnus dot com
- Subject: Re: An alpha egcs bug
- From: hjl at lucon dot org (H.J. Lu)
- Date: Fri, 24 Oct 1997 21:14:57 -0700 (PDT)
- Cc: law at cygnus dot com, egcs at cygnus dot com
> The problem, IMO, is that somewhere in all the myriad SUBREG's that the
> alpha backend generates, reload looses track of what width a pseudo
> actually needs across a spill/reload. It winds up storing 32 bits
> and reading back 64.
>
> The solution that was used in the other case is to have reload always
> spill full registers. It's what should be done again, I think. I
> havn't had time to track it down yet though. And too bad I don't have
> the old test case anymore -- I'd like to see what's different.
>
FWIW, this patch seems to work for me. I have verified it with
egcs 971016 and 971023.
Although those 2 patterns look similar, they have 2 very different
constraints.
--
H.J. Lu (hjl@gnu.ai.mit.edu)
---
Wed Oct 22 07:43:38 1997 H.J. Lu (hjl@gnu.ai.mit.edu)
* config/alpha/alpha.md: Don't allow store in a DFmode
memory location when in SFmode.
Index: config/alpha/alpha.md
===================================================================
RCS file: /home/work/cvs/gnu/egcs/gcc/config/alpha/alpha.md,v
retrieving revision 1.1.1.6
diff -u -r1.1.1.6 alpha.md
--- alpha.md 1997/10/24 01:16:24 1.1.1.6
+++ alpha.md 1997/10/24 23:07:03
@@ -3635,8 +3635,17 @@
}")
(define_insn ""
- [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,f,f,f,m")
- (match_operand:SI 1 "input_operand" "r,J,I,K,L,m,rJ,f,J,m,fG"))]
+ [(set (match_operand:SI 0 "memory_operand" "m,m")
+ (match_operand:SI 1 "reg_or_0_operand" "rJ,fG"))]
+ "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
+ "@
+ stl %r1,%0
+ sts %R1,%0"
+ [(set_attr "type" "st,st")])
+
+(define_insn ""
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,f,f,f")
+ (match_operand:SI 1 "input_operand" "r,J,I,K,L,m,f,J,m"))]
"! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS
&& (register_operand (operands[0], SImode)
|| reg_or_0_operand (operands[1], SImode))"
@@ -3647,12 +3656,10 @@
lda %0,%1
ldah %0,%h1
ldl %0,%1
- stl %r1,%0
cpys %1,%1,%0
cpys $f31,$f31,%0
- lds %0,%1
- sts %R1,%0"
- [(set_attr "type" "ilog,ilog,ilog,iadd,iadd,ld,st,fcpys,fcpys,ld,st")])
+ lds %0,%1"
+ [(set_attr "type" "ilog,ilog,ilog,iadd,iadd,ld,fcpys,fcpys,ld")])
(define_insn ""
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,r,m,f,f,f,m")