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An alpha egcs bug
- To: egcs at cygnus dot com
- Subject: An alpha egcs bug
- From: hjl at lucon dot org (H.J. Lu)
- Date: Wed, 22 Oct 1997 12:48:44 -0700 (PDT)
- Cc: rth at cygnus dot com
Hi,
My previous inline.cc test case shows a serious egcs bugs on alpha.
On alpha, loading an SI/HI/QI integer into register means a very
different thing from storing an SI/HI/QI integer in a memory location.
Loading will result in extending to DI in register, but storing
does not. As the result, you cannot exchange
(set (subreg/s:SI (reg/v:DI 70) 0) (reg:SI 74))
(set (reg:DI 179) (le:DI (reg/v:DI 70) (reg/v:DI 71)))
with
(set (mem:DI (plus:DI (reg:DI 30 $30) (const_int 120))) (reg:SI 1 $1))
(set (reg:DI 6 $6) (mem:DI (plus:DI (reg:DI 30 $30) (const_int 120))))
(set (reg:DI 7 $7) (mem:DI (plus:DI (reg:DI 30 $30) (const_int 128))))
(set (reg:DI 1 $1) (le:DI (reg:DI 6 $6) (reg:DI 7 $7)))
But alpha.md doesn't reflect that detail. With my inline.cc, egcs
generates incorrect asm code. Here is my kludge. It seems to work on
my test case. I hope someone can find a better fix.
BTW, there are quite a few bugs like this in alpha.md. They all should
be fixed.
Thanks.
--
H.J. Lu (hjl@gnu.ai.mit.edu)
---
Wed Oct 22 07:43:38 1997 H.J. Lu (hjl@gnu.ai.mit.edu)
* config/alpha/alpha.md: Don't allow store in a DFmode
memory location when in SFmode.
Index: config/alpha/alpha.md
===================================================================
RCS file: /home/work/cvs/gnu/egcs/gcc/config/alpha/alpha.md,v
retrieving revision 1.1.1.5
diff -u -r1.1.1.5 alpha.md
--- alpha.md 1997/10/17 17:13:20 1.1.1.5
+++ alpha.md 1997/10/22 19:38:46
@@ -3631,8 +3631,15 @@
}")
(define_insn ""
- [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,f,f,f,m")
- (match_operand:SI 1 "input_operand" "r,J,I,K,L,m,rJ,f,J,m,fG"))]
+ [(set (match_operand:SI 0 "memory_operand" "m")
+ (match_operand:SI 1 "reg_or_0_operand" "rJ"))]
+ "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
+ "stl %r1,%0"
+ [(set_attr "type" "st")])
+
+(define_insn ""
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,f,f,f,m")
+ (match_operand:SI 1 "input_operand" "r,J,I,K,L,m,f,J,m,fG"))]
"! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS
&& (register_operand (operands[0], SImode)
|| reg_or_0_operand (operands[1], SImode))"
@@ -3643,12 +3650,11 @@
lda %0,%1
ldah %0,%h1
ldl %0,%1
- stl %r1,%0
cpys %1,%1,%0
cpys $f31,$f31,%0
lds %0,%1
sts %R1,%0"
- [(set_attr "type" "ilog,ilog,ilog,iadd,iadd,ld,st,fcpys,fcpys,ld,st")])
+ [(set_attr "type" "ilog,ilog,ilog,iadd,iadd,ld,fcpys,fcpys,ld,st")])
(define_insn ""
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,r,m,f,f,f,m")