Re: base + index register addressing

[John Carr <jfc at mit dot edu>]

> Current GCC register allocation just cannot handle this, so I have
> "given up" (and just lurk here).

I ran into a similar (but less important) problem working on the IBM
RT port a long time ago.  The output register of RT shift instructions
can be (source register number) or (source register number XOR 1).
Getting the allocator to know about the second version was impractical.
Kenner's comment was "this is fairly easy to do with register coloring
and hard otherwise."

Reload is easier to change than register allocation but it is less
helpful.  allocate_reload_reg should be simple to fix to know about
register allocation interdependencies (given a choice of registers
call a macro to pick the best for the context), and new_spill_reg and
its callers not too difficult.