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Re: [PATCH] Sanitizing the middle-end interface to the back-end for strict alignment
On 8/29/19 11:08 AM, Christophe Lyon wrote:
> On Thu, 29 Aug 2019 at 10:58, Kyrill Tkachov
> <kyrylo.tkachov@foss.arm.com> wrote:
>>
>> Hi Bernd,
>>
>> On 8/28/19 10:36 PM, Bernd Edlinger wrote:
>>> On 8/28/19 2:07 PM, Christophe Lyon wrote:
>>>> Hi,
>>>>
>>>> This patch causes an ICE when building libgcc's unwind-arm.o
>>>> when configuring GCC:
>>>> --target arm-none-linux-gnueabihf --with-mode thumb --with-cpu
>>>> cortex-a15 --with-fpu neon-vfpv4:
>>>>
>>>> The build works for the same target, but --with-mode arm --with-cpu
>>>> cortex a9 --with-fpu vfp
>>>>
>>>> In file included from
>>>> /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/libgcc/config/arm/unwind-arm.c:144:
>>>> /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/libgcc/unwind-arm-common.inc:
>>>> In function 'get_eit_entry':
>>>> /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/libgcc/unwind-arm-common.inc:245:29:
>>>> warning: cast discards 'const' qualifier from pointer target type
>>>> [-Wcast-qual]
>>>> 245 | ucbp->pr_cache.ehtp = (_Unwind_EHT_Header *)&eitp->content;
>>>> | ^
>>>> during RTL pass: expand
>>>> /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/libgcc/unwind-arm-common.inc:
>>>> In function 'unwind_phase2_forced':
>>>> /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/libgcc/unwind-arm-common.inc:319:18:
>>>> internal compiler error: in gen_movdi, at config/arm/arm.md:5235
>>>> 319 | saved_vrs.core = entry_vrs->core;
>>>> | ~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~
>>>> 0x126530f gen_movdi(rtx_def*, rtx_def*)
>>>> /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/config/arm/arm.md:5235
>>>> 0x896d92 insn_gen_fn::operator()(rtx_def*, rtx_def*) const
>>>> /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/recog.h:318
>>>> 0x896d92 emit_move_insn_1(rtx_def*, rtx_def*)
>>>> /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/expr.c:3694
>>>> 0x897083 emit_move_insn(rtx_def*, rtx_def*)
>>>> /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/expr.c:3790
>>>> 0xfc25d6 gen_cpymem_ldrd_strd(rtx_def**)
>>>> /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/config/arm/arm.c:14582
>>>> 0x126a1f1 gen_cpymemqi(rtx_def*, rtx_def*, rtx_def*, rtx_def*)
>>>> /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/config/arm/arm.md:6688
>>>> 0xb0bc08 maybe_expand_insn(insn_code, unsigned int, expand_operand*)
>>>> /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/optabs.c:7440
>>>> 0x89ba1e emit_block_move_via_cpymem
>>>> /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/expr.c:1808
>>>> 0x89ba1e emit_block_move_hints(rtx_def*, rtx_def*, rtx_def*,
>>>> block_op_methods, unsigned int, long, unsigned long, unsigned long,
>>>> unsigned long, bool, bool*)
>>>> /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/expr.c:1627
>>>> 0x89c383 emit_block_move(rtx_def*, rtx_def*, rtx_def*, block_op_methods)
>>>> /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/expr.c:1667
>>>> 0x89fb4e store_expr(tree_node*, rtx_def*, int, bool, bool)
>>>> /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/expr.c:5845
>>>> 0x88c1f9 store_field
>>>> /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/expr.c:7149
>>>> 0x8a0c22 expand_assignment(tree_node*, tree_node*, bool)
>>>> /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/expr.c:5304
>>>> 0x761964 expand_gimple_stmt_1
>>>> /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/cfgexpand.c:3779
>>>> 0x761964 expand_gimple_stmt
>>>> /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/cfgexpand.c:3875
>>>> 0x768583 expand_gimple_basic_block
>>>> /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/cfgexpand.c:5915
>>>> 0x76abc6 execute
>>>> /tmp/6852788_4.tmpdir/aci-gcc-fsf/sources/gcc-fsf/gccsrc/gcc/cfgexpand.c:6538
>>>>
>>>> Christophe
>>>>
>>> Okay, sorry for the breakage.
>>>
>>> What is happening in gen_cpymem_ldrd_strd is of course against the rules:
>>>
>>> It uses emit_move_insn on only 4-byte aligned DI-mode memory operands.
>>>
>>> I have a patch for this, which is able to fix the libgcc build on a cross, but have no
>>> possibility to bootstrap the affected target.
>>>
>>> Could you please help?
>>
>> Well it's good that the sanitisation is catching the bugs!
>>
Yes, more than expected, though ;)
>> Bootstrapping this patch I get another assert with the backtrace:
>
> Thanks for the additional testing, Kyrill!
>
> FWIW, my original report was with a failure to just build GCC for
> cortex-a15. I later got the reports of testing cross-toolchains, and
> saw other problems on cortex-a9 for instance.
> But I guess, you have noticed them with your bootstrap?
> on arm-linux-gnueabi
> gcc.target/arm/aapcs/align4.c (internal compiler error)
> gcc.target/arm/aapcs/align_rec4.c (internal compiler error)
>
This appears to be yet unknown middle-end bug (not fixed by current patch)
$ arm-linux-gnueabihf-gcc align4.c
during RTL pass: expand
In file included from align4.c:22:
align4.c: In function 'testfunc':
abitest.h:73:42: internal compiler error: in gen_movv2si, at config/arm/vec-common.md:30
73 | #define LAST_ARG(type,val,offset) { type __x = val; if (memcmp(&__x, stack+offset, sizeof(type)) != 0) abort(); }
| ^~~
abitest.h:74:30: note: in expansion of macro 'LAST_ARG'
74 | #define ARG(type,val,offset) LAST_ARG(type, val, offset)
| ^~~~~~~~
align4.c:26:3: note: in expansion of macro 'ARG'
26 | ARG (unalignedvec, a, R2)
| ^~~
0x7bb33c gen_movv2si(rtx_def*, rtx_def*)
../../gcc-trunk/gcc/config/arm/vec-common.md:30
0xa4a807 insn_gen_fn::operator()(rtx_def*, rtx_def*) const
../../gcc-trunk/gcc/recog.h:318
0xa4a807 emit_move_insn_1(rtx_def*, rtx_def*)
../../gcc-trunk/gcc/expr.c:3694
0xa4ab94 emit_move_insn(rtx_def*, rtx_def*)
../../gcc-trunk/gcc/expr.c:3790
0xa522bf store_expr(tree_node*, rtx_def*, int, bool, bool)
../../gcc-trunk/gcc/expr.c:5855
0xa52bfd expand_assignment(tree_node*, tree_node*, bool)
../../gcc-trunk/gcc/expr.c:5441
0xa52bfd expand_assignment(tree_node*, tree_node*, bool)
../../gcc-trunk/gcc/expr.c:4982
0x934adf expand_gimple_stmt_1
../../gcc-trunk/gcc/cfgexpand.c:3777
0x934adf expand_gimple_stmt
../../gcc-trunk/gcc/cfgexpand.c:3875
0x93a451 expand_gimple_basic_block
../../gcc-trunk/gcc/cfgexpand.c:5915
0x93c1b6 execute
../../gcc-trunk/gcc/cfgexpand.c:6538
Please submit a full bug report,
with preprocessed source if appropriate.
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.
> (with -march=armv5t: gcc.dg/pr83930.c (internal compiler error))
>
possibly fixed by latest patch.
> on arm-linux-gnueabihf, in addition to align4/align_rec4:
> --with-cpu cortex-a9
> --with-fpu neon-fp16
> gcc.c-torture/execute/pr37573.c -O3 -fomit-frame-pointer
> -funroll-loops -fpeel-loops -ftracer -finline-functions (internal
> compiler error)
> gcc.c-torture/execute/pr37573.c -O3 -g (internal compiler error)
> gcc.dg/vect/fast-math-pr35982.c (internal compiler error)
> gcc.dg/vect/pr55857-1.c (internal compiler error)
> gcc.dg/vect/pr55857-1.c -flto -ffat-lto-objects (internal compiler error)
> gcc.dg/vect/pr55857-2.c (internal compiler error)
> gcc.dg/vect/pr55857-2.c -flto -ffat-lto-objects (internal compiler error)
> gcc.dg/vect/pr57558-2.c (internal compiler error)
> gcc.dg/vect/pr57558-2.c -flto -ffat-lto-objects (internal compiler error)
>
> and even more with other configs
> (http://people.linaro.org/~christophe.lyon/cross-validation/gcc/trunk/274986/report-build-info.html
> may help)
>
> Christophe
>
>>
>> $BUILD/arm-none-linux-gnueabihf/libstdc++-v3/include/ext/concurrence.h:
>> In function '(static initializers for
>> $SRC/libstdc++-v3/libsupc++/eh_alloc.cc)':
>> $BUILD/arm-none-linux-gnueabihf/libstdc++-v3/include/ext/concurrence.h:129:5:
>> internal compiler error: in gen_movv8qi, at config/arm/vec-common.md:29
>> 129 | {
>> | ^
>> 0x14155cb gen_movv8qi(rtx_def*, rtx_def*)
>> $SRC/gcc/config/arm/vec-common.md:29
>> 0x96bb89 insn_gen_fn::operator()(rtx_def*, rtx_def*) const
>> $SRC/gcc/recog.h:318
>> 0x94bc95 emit_move_insn_1(rtx_def*, rtx_def*)
>> $SRC/gcc/expr.c:3694
>> 0x94c05b emit_move_insn(rtx_def*, rtx_def*)
>> $SRC/gcc/expr.c:3790
>> 0x10d5ee5 arm_block_set_aligned_vect
>> $SRC/gcc/config/arm/arm.c:30204
>> 0x10d6b37 arm_block_set_vect
>> $SRC/gcc/config/arm/arm.c:30428
>> 0x10d6caf arm_gen_setmem(rtx_def**)
>> $SRC/gcc/config/arm/arm.c:30458
>> 0x140d7ed gen_setmemsi(rtx_def*, rtx_def*, rtx_def*, rtx_def*)
>> $SRC/gcc/config/arm/arm.md:6687
>> 0xbf0e87 insn_gen_fn::operator()(rtx_def*, rtx_def*, rtx_def*, rtx_def*)
>> const
>> $SRC/gcc/recog.h:320
>> 0xbf0999 maybe_gen_insn(insn_code, unsigned int, expand_operand*)
>> $SRC/gcc/optabs.c:7409
>> 0xbf0b87 maybe_expand_insn(insn_code, unsigned int, expand_operand*)
>> $SRC/gcc/optabs.c:7440
>> 0x94a709 set_storage_via_setmem(rtx_def*, rtx_def*, rtx_def*, unsigned
>> int, unsigned int, long long, unsigned long long, unsigned long long,
>> unsigned long long)
>> $SRC/gcc/expr.c:3168
>> 0x94a059 clear_storage_hints(rtx_def*, rtx_def*, block_op_methods,
>> unsigned int, long long, unsigned long long, unsigned long long,
>> unsigned long long)
>> $SRC/gcc/expr.c:3037
>> 0x94a137 clear_storage(rtx_def*, rtx_def*, block_op_methods)
>> $SRC/gcc/expr.c:3058
>> 0x9537c5 store_constructor
>> $SRC/gcc/expr.c:6333
>> 0x957227 store_field
>> $SRC/gcc/expr.c:7145
>> 0x94fde1 expand_assignment(tree_node*, tree_node*, bool)
>> $SRC/gcc/expr.c:5301
>> 0x815e25 expand_gimple_stmt_1
>> $SRC/gcc/cfgexpand.c:3777
>> 0x81611d expand_gimple_stmt
>> $SRC/gcc/cfgexpand.c:3875
>> 0x81cd61 expand_gimple_basic_block
>> $SRC/gcc/cfgexpand.c:5915
>>
>> Looks to me like arm_gen_setmem needs similar fixes to gen_cpymem_ldrd_strd?
>>
Yes, indeed, see attached patch.
This seems to fix the bootstrap, but at least one other error remains,
however I think those do hopefully not break the boot-strap and can be
fixed with follow-up patches.
Christophe can you please track the remaining regressions, that would be
very helpful.
Attached is an updated patch version which should un-break the bootstrap issues.
Is it OK for trunk?
Thanks
Bernd.
2019-08-29 Bernd Edlinger <bernd.edlinger@hotmail.de>
* config/arm/arm.md (unaligned_loaddi,
unaligned_storedi): New unspec insn patterns.
* config/arm/neon.md (unaligned_storev8qi): Likewise.
* config/arm/arm.c (gen_cpymem_ldrd_strd): Use unaligned_loaddi
and unaligned_storedi for 4-byte aligned memory.
(arm_block_set_aligned_vect): Use unaligned_storev8qi for
4-byte aligned memory.
Index: gcc/config/arm/arm.c
===================================================================
--- gcc/config/arm/arm.c (revision 274987)
+++ gcc/config/arm/arm.c (working copy)
@@ -14578,8 +14578,10 @@ gen_cpymem_ldrd_strd (rtx *operands)
low_reg = gen_lowpart (SImode, reg0);
hi_reg = gen_highpart_mode (SImode, DImode, reg0);
}
- if (src_aligned)
- emit_move_insn (reg0, src);
+ if (MEM_ALIGN (src) >= 2 * BITS_PER_WORD)
+ emit_move_insn (reg0, src);
+ else if (src_aligned)
+ emit_insn (gen_unaligned_loaddi (reg0, src));
else
{
emit_insn (gen_unaligned_loadsi (low_reg, src));
@@ -14587,8 +14589,10 @@ gen_cpymem_ldrd_strd (rtx *operands)
emit_insn (gen_unaligned_loadsi (hi_reg, src));
}
- if (dst_aligned)
- emit_move_insn (dst, reg0);
+ if (MEM_ALIGN (dst) >= 2 * BITS_PER_WORD)
+ emit_move_insn (dst, reg0);
+ else if (dst_aligned)
+ emit_insn (gen_unaligned_storedi (dst, reg0));
else
{
emit_insn (gen_unaligned_storesi (dst, low_reg));
@@ -30197,7 +30201,10 @@ arm_block_set_aligned_vect (rtx dstbase,
{
addr = plus_constant (Pmode, dst, i);
mem = adjust_automodify_address (dstbase, mode, addr, offset + i);
- emit_move_insn (mem, reg);
+ if (MEM_ALIGN (mem) >= 2 * BITS_PER_WORD)
+ emit_move_insn (mem, reg);
+ else
+ emit_insn (gen_unaligned_storev8qi (mem, reg));
}
/* Handle single word leftover by shifting 4 bytes back. We can
@@ -30211,7 +30218,7 @@ arm_block_set_aligned_vect (rtx dstbase,
if (align > UNITS_PER_WORD)
set_mem_align (mem, BITS_PER_UNIT * UNITS_PER_WORD);
- emit_move_insn (mem, reg);
+ emit_insn (gen_unaligned_storev8qi (mem, reg));
}
/* Handle (0, 4), (4, 8) bytes leftover by shifting bytes back.
We have to use unaligned access for this case. */
Index: gcc/config/arm/arm.md
===================================================================
--- gcc/config/arm/arm.md (revision 274987)
+++ gcc/config/arm/arm.md (working copy)
@@ -3963,6 +3963,17 @@
; ARMv6+ unaligned load/store instructions (used for packed structure accesses).
+(define_insn "unaligned_loaddi"
+ [(set (match_operand:DI 0 "s_register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "memory_operand" "m")]
+ UNSPEC_UNALIGNED_LOAD))]
+ "TARGET_32BIT && TARGET_LDRD"
+ "*
+ return output_move_double (operands, true, NULL);
+ "
+ [(set_attr "length" "8")
+ (set_attr "type" "load_8")])
+
(define_insn "unaligned_loadsi"
[(set (match_operand:SI 0 "s_register_operand" "=l,l,r")
(unspec:SI [(match_operand:SI 1 "memory_operand" "m,Uw,m")]
@@ -4008,6 +4019,17 @@
(set_attr "predicable_short_it" "no,yes,no")
(set_attr "type" "load_byte")])
+(define_insn "unaligned_storedi"
+ [(set (match_operand:DI 0 "memory_operand" "=m")
+ (unspec:DI [(match_operand:DI 1 "s_register_operand" "r")]
+ UNSPEC_UNALIGNED_STORE))]
+ "TARGET_32BIT && TARGET_LDRD"
+ "*
+ return output_move_double (operands, true, NULL);
+ "
+ [(set_attr "length" "8")
+ (set_attr "type" "store_8")])
+
(define_insn "unaligned_storesi"
[(set (match_operand:SI 0 "memory_operand" "=m,Uw,m")
(unspec:SI [(match_operand:SI 1 "s_register_operand" "l,l,r")]
Index: gcc/config/arm/neon.md
===================================================================
--- gcc/config/arm/neon.md (revision 274987)
+++ gcc/config/arm/neon.md (working copy)
@@ -23,6 +23,17 @@
;; type attribute definitions.
(define_attr "vqh_mnem" "vadd,vmin,vmax" (const_string "vadd"))
+(define_insn "unaligned_storev8qi"
+ [(set (match_operand:V8QI 0 "memory_operand" "=Un")
+ (unspec:V8QI [(match_operand:V8QI 1 "s_register_operand" "w")]
+ UNSPEC_UNALIGNED_STORE))]
+ "TARGET_NEON"
+ "*
+ return output_move_neon (operands);
+ "
+ [(set_attr "length" "4")
+ (set_attr "type" "neon_store1_1reg")])
+
(define_insn "*neon_mov<mode>"
[(set (match_operand:VDX 0 "nonimmediate_operand"
"=w,Un,w, w, w, ?r,?w,?r, ?Us,*r")