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Re: [PATCH 1/2] gcc/riscv: Include more registers in SIBCALL_REGS

From: Jim Wilson <jimw at sifive dot com>
To: Andrew Burgess <andrew dot burgess at embecosm dot com>
Cc: GCC Patches <gcc-patches at gcc dot gnu dot org>
Date: Thu, 22 Aug 2019 22:30:46 -0700
Subject: Re: [PATCH 1/2] gcc/riscv: Include more registers in SIBCALL_REGS
References: <cover.1566241794.git.andrew.burgess@embecosm.com> <b8da34c1fe62f15164194ba5613e4533c30d300a.1566241796.git.andrew.burgess@embecosm.com>

On Mon, Aug 19, 2019 at 12:15 PM Andrew Burgess
<andrew.burgess@embecosm.com> wrote:
> I don't see any reason why we couldn't add t1, and a0 to a7 into this
> set, and this is what this patch does.

SIBCALL_REGS already includes t1 and t2.  It is t0 aka x5 that is
missing.  I think this is wrong.  As Andrew mentioned, this will
penalize any target that has a call-stack aware branch predictor.  We
could add a tune flag for that, but it doesn't seem worth the effort.
Adding the other regs a0 to a7 is OK.  They won't be used unless they
are available.  This is OK without the t0/x5 change.

Jim

Follow-Ups:
- Re: [PATCH 1/2] gcc/riscv: Include more registers in SIBCALL_REGS
  - From: Jim Wilson

References:
- [PATCH 0/2] RISCV: Reduce code size when compiling with -msave-restore
  - From: Andrew Burgess
- [PATCH 1/2] gcc/riscv: Include more registers in SIBCALL_REGS
  - From: Andrew Burgess

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