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[PATCH], Fix V1TI in Altivec regs on old systems

This is a little corner case that I noticed in my rewrite of the RELOAD_REG
stuff for the future machine.

I was testing what registers were allowed in what registers for various systems
(power5 through power9 for big endian on both 32 & 64-bit systems, and
power8/power9 for little endian systems).  I was using the debug flag
-mdebug=reg which dumps out the reg_addr information (among other things).  I
noticed on power5 that the V1TImode mode is allowed in Altivec registers, even
though power5 doesn't have Altivec registers.

While it doesn't seem to effect anything (I couldn't create a test case that
failed), it is a small nit that should be fixed.  The test for TARGET_VADDUQM
matches a test earlier in the function where VSX registers are checked.

I have done a bootstrap on a little endian power8 and there were no regressions
in the bootstrap or make check.  I also verified via -mdebug=reg that V1TI mode
is marked as being valid in the Altivec registers with -mcpu=power5.  Can I
check this into the trunk?

2019-08-20  Michael Meissner  <>

	* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok_uncached):
	Don't allow V1TImode in Altivec registers on pre-altivec systems.

Index: gcc/config/rs6000/rs6000.c
--- gcc/config/rs6000/rs6000.c	(revision 274635)
+++ gcc/config/rs6000/rs6000.c	(working copy)
@@ -1874,7 +1874,7 @@ rs6000_hard_regno_mode_ok_uncached (int
   /* AltiVec only in AldyVec registers.  */
   if (ALTIVEC_REGNO_P (regno))
     return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
-	    || mode == V1TImode);
+	    || (TARGET_VADDUQM && mode == V1TImode));
   /* We cannot put non-VSX TImode or PTImode anywhere except general register
      and it must be able to fit within the register set.  */

Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email:, phone: +1 (978) 899-4797

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