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[PATCH v2 13/18] Use MEM_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh MEM


2019-08-05  Arvind Sankar  <nivedita@alum.mit.edu>

	gcc/ChangeLog:

	* combine.c: Convert GET_CODE (..) == MEM to MEM_P (..).
	* config/aarch64/aarch64-simd.md: Likewise.
	* config/aarch64/aarch64-sve.md: Likewise.
	* config/aarch64/aarch64.c: Likewise.
	* config/aarch64/aarch64.md: Likewise.
	* config/arc/arc.c: Likewise.
	* config/arc/predicates.md: Likewise.
	* config/arc/simdext.md: Likewise.
	* config/arm/arm.c: Likewise.
	* config/bfin/bfin.c: Likewise.
	* config/bfin/bfin.md: Likewise.
	* config/c6x/c6x.c: Likewise.
	* config/c6x/c6x.md: Likewise.
	* config/cr16/cr16.c: Likewise.
	* config/cr16/cr16.h: Likewise.
	* config/cr16/predicates.md: Likewise.
	* config/csky/csky.c: Likewise.
	* config/csky/csky.md: Likewise.
	* config/csky/predicates.md: Likewise.
	* config/darwin.c: Likewise.
	* config/epiphany/epiphany.md: Likewise.
	* config/epiphany/predicates.md: Likewise.
	* config/fr30/fr30.md: Likewise.
	* config/fr30/predicates.md: Likewise.
	* config/frv/frv.c: Likewise.
	* config/frv/frv.md: Likewise.
	* config/frv/predicates.md: Likewise.
	* config/h8300/h8300.c: Likewise.
	* config/h8300/h8300.md: Likewise.
	* config/h8300/predicates.md: Likewise.
	* config/i386/i386-expand.c: Likewise.
	* config/ia64/ia64.c: Likewise.
	* config/ia64/ia64.md: Likewise.
	* config/ia64/predicates.md: Likewise.
	* config/iq2000/iq2000.c: Likewise.
	* config/iq2000/iq2000.md: Likewise.
	* config/iq2000/predicates.md: Likewise.
	* config/lm32/lm32.md: Likewise.
	* config/m32c/m32c.c: Likewise.
	* config/m32c/predicates.md: Likewise.
	* config/m68k/m68k.c: Likewise.
	* config/m68k/m68k.md: Likewise.
	* config/m68k/predicates.md: Likewise.
	* config/mcore/mcore.c: Likewise.
	* config/mcore/mcore.md: Likewise.
	* config/mcore/predicates.md: Likewise.
	* config/microblaze/microblaze.c: Likewise.
	* config/microblaze/microblaze.md: Likewise.
	* config/mmix/mmix.md: Likewise.
	* config/msp430/msp430.c: Likewise.
	* config/nds32/nds32-fp-as-gp.c: Likewise.
	* config/nds32/nds32-multiple.md: Likewise.
	* config/nds32/nds32-predicates.c: Likewise.
	* config/nios2/nios2.c: Likewise.
	* config/nvptx/nvptx.c: Likewise.
	* config/pa/pa.c: Likewise.
	* config/pa/pa.md: Likewise.
	* config/pdp11/pdp11.c: Likewise.
	* config/pru/predicates.md: Likewise.
	* config/pru/pru.md: Likewise.
	* config/rl78/rl78.c: Likewise.
	* config/rx/rx.c: Likewise.
	* config/s390/predicates.md: Likewise.
	* config/s390/s390.c: Likewise.
	* config/s390/s390.md: Likewise.
	* config/sparc/predicates.md: Likewise.
	* config/sparc/sparc.c: Likewise.
	* config/spu/spu.c: Likewise.
	* config/spu/spu.md: Likewise.
	* config/stormy16/predicates.md: Likewise.
	* config/v850/predicates.md: Likewise.
	* config/v850/v850.c: Likewise.
	* config/visium/visium.c: Likewise.
	* config/xtensa/xtensa.c: Likewise.
	* dbxout.c: Likewise.
	* df-scan.c: Likewise.
	* fwprop.c: Likewise.
	* ifcvt.c: Likewise.
	* simplify-rtx.c: Likewise.
	* var-tracking.c: Likewise.

 80 files changed, 478 insertions(+), 478 deletions(-)

diff --git a/gcc/combine.c b/gcc/combine.c
index b175ed9c4a0..a7af1ace40b 100644
--- a/gcc/combine.c
+++ b/gcc/combine.c
@@ -2779,13 +2779,13 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
       if ((set0 = single_set (i0))
 	  /* Ensure the source of SET0 is a MEM, possibly buried inside
 	     an extension.  */
-	  && (GET_CODE (SET_SRC (set0)) == MEM
+	  && (MEM_P (SET_SRC (set0))
 	      || ((GET_CODE (SET_SRC (set0)) == ZERO_EXTEND
 		   || GET_CODE (SET_SRC (set0)) == SIGN_EXTEND)
-		  && GET_CODE (XEXP (SET_SRC (set0), 0)) == MEM))
+		  && MEM_P (XEXP (SET_SRC (set0), 0))))
 	  && (set3 = single_set (i3))
 	  /* Ensure the destination of SET3 is a MEM.  */
-	  && GET_CODE (SET_DEST (set3)) == MEM
+	  && MEM_P (SET_DEST (set3))
 	  /* Would it be better to extract the base address for the MEM
 	     in SET3 and look for that?  I don't have cases where it matters
 	     but I could envision such cases.  */
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 0fe7ef60d33..b36cfce0d92 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -29,7 +29,7 @@
      a stp in DI mode, so we check the validity of that.
      If the mode is 8 bytes wide, then we will do doing a
      normal str, so the check need not apply.  */
-  if (GET_CODE (operands[0]) == MEM
+  if (MEM_P (operands[0])
       && !(aarch64_simd_imm_zero (operands[1], <MODE>mode)
 	   && ((known_eq (GET_MODE_SIZE (<MODE>mode), 16)
 		&& aarch64_mem_pair_operand (operands[0], DImode))
diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md
index e489afbdde9..3f65d5f6604 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -438,7 +438,7 @@
 	(match_operand:PRED_ALL 1 "general_operand"))]
   "TARGET_SVE"
   {
-    if (GET_CODE (operands[0]) == MEM)
+    if (MEM_P (operands[0]))
       operands[1] = force_reg (<MODE>mode, operands[1]);
   }
 )
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 70cac11c257..f54a0d462a8 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -2099,7 +2099,7 @@ aarch64_load_symref_appropriately (rtx dest, rtx imm,
 	/* The operand is expected to be MEM.  Whenever the related insn
 	   pattern changed, above code which calculate mem should be
 	   updated.  */
-	gcc_assert (GET_CODE (mem) == MEM);
+	gcc_assert (MEM_P (mem));
 	MEM_READONLY_P (mem) = 1;
 	MEM_NOTRAP_P (mem) = 1;
 	emit_insn (insn);
@@ -2142,7 +2142,7 @@ aarch64_load_symref_appropriately (rtx dest, rtx imm,
 	    mem = XVECEXP (XEXP (SET_SRC (insn), 0), 0, 0);
 	  }
 
-	gcc_assert (GET_CODE (mem) == MEM);
+	gcc_assert (MEM_P (mem));
 	MEM_READONLY_P (mem) = 1;
 	MEM_NOTRAP_P (mem) = 1;
 	emit_insn (insn);
@@ -8084,7 +8084,7 @@ aarch64_print_operand (FILE *f, rtx x, int code)
       {
 	machine_mode mode = GET_MODE (x);
 
-	if (GET_CODE (x) != MEM
+	if (!MEM_P (x)
 	    || (code == 'y' && maybe_ne (GET_MODE_SIZE (mode), 16)))
 	  {
 	    output_operand_lossage ("invalid operand for '%%%c'", code);
@@ -18118,20 +18118,20 @@ fusion_load_store (rtx_insn *insn, rtx *base, rtx *offset)
     {
       fusion = SCHED_FUSION_LD_SIGN_EXTEND;
       src = XEXP (src, 0);
-      if (GET_CODE (src) != MEM || GET_MODE (src) != SImode)
+      if (!MEM_P (src) || GET_MODE (src) != SImode)
 	return SCHED_FUSION_NONE;
     }
   else if (GET_CODE (src) == ZERO_EXTEND)
     {
       fusion = SCHED_FUSION_LD_ZERO_EXTEND;
       src = XEXP (src, 0);
-      if (GET_CODE (src) != MEM || GET_MODE (src) != SImode)
+      if (!MEM_P (src) || GET_MODE (src) != SImode)
 	return SCHED_FUSION_NONE;
     }
 
-  if (GET_CODE (src) == MEM && REG_P (dest))
+  if (MEM_P (src) && REG_P (dest))
     extract_base_offset_in_addr (src, base, offset);
-  else if (GET_CODE (dest) == MEM && (REG_P (src) || src == const0_rtx))
+  else if (MEM_P (dest) && (REG_P (src) || src == const0_rtx))
     {
       fusion = SCHED_FUSION_ST;
       extract_base_offset_in_addr (dest, base, offset);
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 1fe96d5f772..ff3addfe615 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -1020,7 +1020,7 @@
 	(match_operand:SHORT 1 "general_operand"))]
   ""
   "
-    if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx)
+    if (MEM_P (operands[0]) && operands[1] != const0_rtx)
       operands[1] = force_reg (<MODE>mode, operands[1]);
 
     if (GET_CODE (operands[1]) == CONST_POLY_INT)
@@ -1082,7 +1082,7 @@
 	&& aarch64_split_dimode_const_store (operands[0], operands[1]))
       DONE;
 
-    if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx)
+    if (MEM_P (operands[0]) && operands[1] != const0_rtx)
       operands[1] = force_reg (<MODE>mode, operands[1]);
 
     /* FIXME: RR we still need to fix up what we are doing with
@@ -1184,7 +1184,7 @@
 	(match_operand:TI 1 "general_operand"))]
   ""
   "
-    if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx)
+    if (MEM_P (operands[0]) && operands[1] != const0_rtx)
       operands[1] = force_reg (TImode, operands[1]);
 
     if (GET_CODE (operands[1]) == CONST_POLY_INT)
@@ -1245,7 +1245,7 @@
 	FAIL;
       }
 
-    if (GET_CODE (operands[0]) == MEM
+    if (MEM_P (operands[0])
         && ! (CONST_DOUBLE_P (operands[1])
 	      && aarch64_float_const_zero_rtx_p (operands[1])))
       operands[1] = force_reg (<MODE>mode, operands[1]);
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 5a06d94d5f7..e79f36761b2 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -925,7 +925,7 @@ arc_secondary_reload_conv (rtx reg, rtx mem, rtx scratch, bool store_p)
 {
   rtx addr;
 
-  gcc_assert (GET_CODE (mem) == MEM);
+  gcc_assert (MEM_P (mem));
   addr = XEXP (mem, 0);
 
   /* Large offset: use a move.  FIXME: ld ops accepts limms as
@@ -4595,7 +4595,7 @@ arc_print_operand (FILE *file, rtx x, int code)
 	 register or memory.  */
       if (REG_P (x))
 	fputs (reg_names[REGNO (x)+1], file);
-      else if (GET_CODE (x) == MEM)
+      else if (MEM_P (x))
 	{
 	  fputc ('[', file);
 
@@ -4721,7 +4721,7 @@ arc_print_operand (FILE *file, rtx x, int code)
       }
     case 'U' :
       /* Output a load/store with update indicator if appropriate.  */
-      if (GET_CODE (x) == MEM)
+      if (MEM_P (x))
 	{
 	  rtx addr = XEXP (x, 0);
 	  switch (GET_CODE (addr))
@@ -4779,7 +4779,7 @@ arc_print_operand (FILE *file, rtx x, int code)
     case 'V' :
       /* Output cache bypass indicator for a load/store insn.  Volatile memory
 	 refs are defined to use the cache bypass mechanism.  */
-      if (GET_CODE (x) == MEM)
+      if (MEM_P (x))
 	{
 	  if ((MEM_VOLATILE_P (x) && !TARGET_VOLATILE_CACHE_SET)
 	      || arc_is_uncached_mem_p (x))
@@ -8701,7 +8701,7 @@ compact_sda_memory_operand (rtx op, machine_mode mode, bool short_p)
   int mask = 0;
 
   /* Eliminate non-memory operations.  */
-  if (GET_CODE (op) != MEM)
+  if (!MEM_P (op))
     return false;
 
   if (mode == VOIDmode)
@@ -10920,7 +10920,7 @@ compact_memory_operand_p (rtx op, machine_mode mode,
   int size, off;
 
   /* Eliminate non-memory operations.  */
-  if (GET_CODE (op) != MEM)
+  if (!MEM_P (op))
     return 0;
 
   /* .di instructions have no 16-bit form.  */
diff --git a/gcc/config/arc/predicates.md b/gcc/config/arc/predicates.md
index 01bfc1b9547..a5537ec73e4 100644
--- a/gcc/config/arc/predicates.md
+++ b/gcc/config/arc/predicates.md
@@ -291,7 +291,7 @@
     case SUBREG :
       /* (subreg (mem ...) ...) can occur here if the inner part was once a
 	 pseudo-reg and is now a stack slot.  */
-      if (GET_CODE (SUBREG_REG (op)) == MEM)
+      if (MEM_P (SUBREG_REG (op)))
 	return address_operand (XEXP (SUBREG_REG (op), 0), mode);
       else
 	return register_operand (op, mode);
@@ -315,7 +315,7 @@
     case SUBREG :
       /* (subreg (mem ...) ...) can occur here if the inner part was once a
 	 pseudo-reg and is now a stack slot.  */
-      if (GET_CODE (SUBREG_REG (op)) == MEM)
+      if (MEM_P (SUBREG_REG (op)))
 	return address_operand (XEXP (SUBREG_REG (op), 0), mode);
       else
 	return register_operand (op, mode);
@@ -355,7 +355,7 @@
     case SUBREG :
       /* (subreg (mem ...) ...) can occur here if the inner part was once a
 	 pseudo-reg and is now a stack slot.  */
-      if (GET_CODE (SUBREG_REG (op)) == MEM)
+      if (MEM_P (SUBREG_REG (op)))
 	return address_operand (XEXP (SUBREG_REG (op), 0), mode);
       else
 	return dest_reg_operand (op, mode);
@@ -398,7 +398,7 @@
 ;; and only the standard movXX patterns are set up to handle them.
 (define_predicate "nonvol_nonimm_operand"
   (and (match_code "subreg, reg, mem")
-       (match_test "(GET_CODE (op) != MEM || !MEM_VOLATILE_P (op)) && nonimmediate_operand (op, mode)")
+       (match_test "(!MEM_P (op) || !MEM_VOLATILE_P (op)) && nonimmediate_operand (op, mode)")
        (match_test "!arc_is_uncached_mem_p (op)"))
 )
 
@@ -652,7 +652,7 @@
   if ((GET_MODE (op) != mode) && (mode != VOIDmode))
     return 0;
 
-  if ((GET_CODE (op) == MEM)
+  if ((MEM_P (op))
       && (mode == V8HImode)
       && REG_P (XEXP (op,0)))
     return 1;
diff --git a/gcc/config/arc/simdext.md b/gcc/config/arc/simdext.md
index 53a0a90ef3b..9a450fbe446 100644
--- a/gcc/config/arc/simdext.md
+++ b/gcc/config/arc/simdext.md
@@ -163,7 +163,7 @@
 {
   /* Everything except mem = const or mem = mem can be done easily.  */
 
-  if (GET_CODE (operands[0]) == MEM && GET_CODE(operands[1]) == MEM)
+  if (MEM_P (operands[0]) && MEM_P (operands[1]))
     operands[1] = force_reg (V8HImode, operands[1]);
 }")
 
@@ -213,7 +213,7 @@
 (define_insn "movv8hi_insn"
   [(set (match_operand:V8HI 0 "vector_register_or_memory_operand" "=v,m,v")
 	(match_operand:V8HI 1 "vector_register_or_memory_operand" "m,v,v"))]
-  "TARGET_SIMD_SET && !(GET_CODE (operands[0]) == MEM && GET_CODE(operands[1]) == MEM)"
+  "TARGET_SIMD_SET && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
   "@
     vld128r %0, %1
     vst128r %1, %0
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 2a5359c26ec..fd18f92b6ec 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -31207,12 +31207,12 @@ fusion_load_store (rtx_insn *insn, rtx *base, rtx *offset, bool *is_load)
 
   src = SET_SRC (x);
   dest = SET_DEST (x);
-  if (REG_P (src) && GET_CODE (dest) == MEM)
+  if (REG_P (src) && MEM_P (dest))
     {
       *is_load = false;
       extract_base_offset_in_addr (dest, base, offset);
     }
-  else if (GET_CODE (src) == MEM && REG_P (dest))
+  else if (MEM_P (src) && REG_P (dest))
     {
       *is_load = true;
       extract_base_offset_in_addr (src, base, offset);
diff --git a/gcc/config/bfin/bfin.c b/gcc/config/bfin/bfin.c
index 716e7345d50..7ae604716e6 100644
--- a/gcc/config/bfin/bfin.c
+++ b/gcc/config/bfin/bfin.c
@@ -1217,7 +1217,7 @@ bfin_delegitimize_address (rtx orig_x)
 {
   rtx x = orig_x;
 
-  if (GET_CODE (x) != MEM)
+  if (!MEM_P (x))
     return orig_x;
 
   x = XEXP (x, 0);
@@ -1324,7 +1324,7 @@ print_address_operand (FILE *file, rtx x)
       break;
 
     default:
-      gcc_assert (GET_CODE (x) != MEM);
+      gcc_assert (!MEM_P (x));
       print_operand (file, x, 0);
       break;
     }
@@ -1915,7 +1915,7 @@ emit_pic_move (rtx *operands, machine_mode mode ATTRIBUTE_UNUSED)
   rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
 
   gcc_assert (!TARGET_FDPIC || !(reload_in_progress || reload_completed));
-  if (GET_CODE (operands[0]) == MEM && SYMBOLIC_CONST (operands[1]))
+  if (MEM_P (operands[0]) && SYMBOLIC_CONST (operands[1]))
     operands[1] = force_reg (SImode, operands[1]);
   else
     operands[1] = legitimize_pic_address (operands[1], temp,
@@ -1947,7 +1947,7 @@ expand_move (rtx *operands, machine_mode mode)
       op1 = XEXP (op, 1);
       if (!insn_data[CODE_FOR_addsi3].operand[2].predicate (op1, mode))
 	op1 = force_reg (mode, op1);
-      if (GET_CODE (dest) == MEM)
+      if (MEM_P (dest))
 	dest = gen_reg_rtx (mode);
       emit_insn (gen_addsi3 (dest, op0, op1));
       if (dest == operands[0])
@@ -1957,7 +1957,7 @@ expand_move (rtx *operands, machine_mode mode)
   /* Don't generate memory->memory or constant->memory moves, go through a
      register */
   else if ((reload_in_progress | reload_completed) == 0
-	   && GET_CODE (operands[0]) == MEM
+	   && MEM_P (operands[0])
     	   && !REG_P (operands[1]))
     operands[1] = force_reg (mode, operands[1]);
   return false;
@@ -1978,7 +1978,7 @@ split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
 
       /* simplify_subreg refuse to split volatile memory addresses,
          but we still have to handle it.  */
-      if (GET_CODE (op) == MEM)
+      if (MEM_P (op))
 	{
 	  lo_half[num] = adjust_address (op, SImode, 0);
 	  hi_half[num] = adjust_address (op, SImode, 4);
@@ -3045,7 +3045,7 @@ analyze_push_multiple_operation (rtx op)
 
       src = SET_SRC (t);
       dest = SET_DEST (t);
-      if (GET_CODE (dest) != MEM || ! REG_P (src))
+      if (!MEM_P (dest) || ! REG_P (src))
 	return 0;
       dest = XEXP (dest, 0);
       if (GET_CODE (dest) != PLUS
@@ -3114,7 +3114,7 @@ analyze_pop_multiple_operation (rtx op)
 
       src = SET_SRC (t);
       dest = SET_DEST (t);
-      if (GET_CODE (src) != MEM || ! REG_P (dest))
+      if (!MEM_P (src) || ! REG_P (dest))
 	return 0;
       src = XEXP (src, 0);
 
@@ -4297,7 +4297,7 @@ indirect_call_p (rtx pat)
     pat = SET_SRC (pat);
   gcc_assert (GET_CODE (pat) == CALL);
   pat = XEXP (pat, 0);
-  gcc_assert (GET_CODE (pat) == MEM);
+  gcc_assert (MEM_P (pat));
   pat = XEXP (pat, 0);
   
   return REG_P (pat);
diff --git a/gcc/config/bfin/bfin.md b/gcc/config/bfin/bfin.md
index 2c70db8b39b..627b5a4b47c 100644
--- a/gcc/config/bfin/bfin.md
+++ b/gcc/config/bfin/bfin.md
@@ -505,7 +505,7 @@
 (define_insn_and_split "movdi_insn"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=x,mx,r")
 	(match_operand:DI 1 "general_operand" "iFx,r,mx"))]
-  "GET_CODE (operands[0]) != MEM || REG_P (operands[1])"
+  "!MEM_P (operands[0]) || REG_P (operands[1])"
   "#"
   "reload_completed"
   [(set (match_dup 2) (match_dup 3))
@@ -607,7 +607,7 @@
 (define_insn "*movsi_insn"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=da,x,da,y,da,x,x,x,da,mr")
 	(match_operand:SI 1 "general_operand" "da,x,y,da,xKs7,xKsh,xKuh,ix,mr,da"))]
-  "GET_CODE (operands[0]) != MEM || REG_P (operands[1])"
+  "!MEM_P (operands[0]) || REG_P (operands[1])"
  "@
    %0 = %1;
    %0 = %1;
@@ -647,7 +647,7 @@
   [(set (match_operand:V2HI 0 "nonimmediate_operand" "=da,da,d,dm")
         (match_operand:V2HI 1 "general_operand" "i,di,md,d"))]
 
-  "GET_CODE (operands[0]) != MEM || REG_P (operands[1])"
+  "!MEM_P (operands[0]) || REG_P (operands[1])"
   "@
    #
    %0 = %1;
@@ -669,7 +669,7 @@
 (define_insn "*movhi_insn"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=x,da,x,d,mr")
         (match_operand:HI 1 "general_operand" "x,xKs7,xKsh,mr,d"))]
-  "GET_CODE (operands[0]) != MEM || REG_P (operands[1])"
+  "!MEM_P (operands[0]) || REG_P (operands[1])"
 {
   static const char *templates[] = {
     "%0 = %1;",
@@ -693,7 +693,7 @@
 (define_insn "*movqi_insn"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=x,da,x,d,mr")
         (match_operand:QI 1 "general_operand" "x,xKs7,xKsh,mr,d"))]
-  "GET_CODE (operands[0]) != MEM || REG_P (operands[1])"
+  "!MEM_P (operands[0]) || REG_P (operands[1])"
   "@
    %0 = %1;
    %0 = %1 (X);
@@ -706,7 +706,7 @@
 (define_insn "*movsf_insn"
   [(set (match_operand:SF 0 "nonimmediate_operand" "=x,x,da,mr")
         (match_operand:SF 1 "general_operand" "x,Fx,mr,da"))]
-  "GET_CODE (operands[0]) != MEM || REG_P (operands[1])"
+  "!MEM_P (operands[0]) || REG_P (operands[1])"
   "@
    %0 = %1;
    #
@@ -717,7 +717,7 @@
 (define_insn_and_split "movdf_insn"
   [(set (match_operand:DF 0 "nonimmediate_operand" "=x,mx,r")
 	(match_operand:DF 1 "general_operand" "iFx,r,mx"))]
-  "GET_CODE (operands[0]) != MEM || REG_P (operands[1])"
+  "!MEM_P (operands[0]) || REG_P (operands[1])"
   "#"
   "reload_completed"
   [(set (match_dup 2) (match_dup 3))
diff --git a/gcc/config/c6x/c6x.c b/gcc/config/c6x/c6x.c
index dab63cb3011..938e42f24d6 100644
--- a/gcc/config/c6x/c6x.c
+++ b/gcc/config/c6x/c6x.c
@@ -1375,7 +1375,7 @@ expand_move (rtx *operands, machine_mode mode)
   rtx op = operands[1];
 
   if ((reload_in_progress | reload_completed) == 0
-      && GET_CODE (dest) == MEM && !REG_P (op))
+      && MEM_P (dest) && !REG_P (op))
     operands[1] = force_reg (mode, op);
   else if (mode == SImode && symbolic_operand (op, SImode))
     {
@@ -1973,7 +1973,7 @@ c6x_print_address_operand (FILE *file, rtx x, machine_mode mem_mode)
       break;
 
     default:
-      gcc_assert (GET_CODE (x) != MEM);
+      gcc_assert (!MEM_P (x));
       c6x_print_operand (file, x, 0);
       break;
     }
diff --git a/gcc/config/c6x/c6x.md b/gcc/config/c6x/c6x.md
index 1404363f8f8..f108c671796 100644
--- a/gcc/config/c6x/c6x.md
+++ b/gcc/config/c6x/c6x.md
@@ -602,7 +602,7 @@
         "=a,b, a, b, ab, ab,a,?a, b,?b, Q, R, R, Q")
        (match_operand:QIHIM 1 "general_operand"
          "a,b,?b,?a,Is5,IsB,Q, R, R, Q, a,?a, b,?b"))]
-  "GET_CODE (operands[0]) != MEM || REG_P (operands[1])"
+  "!MEM_P (operands[0]) || REG_P (operands[1])"
  "@
   %|%.\\tmv\\t%$\\t%1, %0
   %|%.\\tmv\\t%$\\t%1, %0
@@ -631,7 +631,7 @@
         "=a,b, a, b, ab, ab,a,b,ab,a,?a, b,?b, Q, R, R, Q")
        (match_operand:SISFVM 1 "general_operand"
          "a,b,?b,?a,Is5,IsB,S0,S0,Si,Q, R, R, Q, a,?a, b,?b"))]
-  "(GET_CODE (operands[0]) != MEM || REG_P (operands[1])
+  "(!MEM_P (operands[0]) || REG_P (operands[1])
     || (SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1]))))"
  "@
   %|%.\\tmv\\t%$\\t%1, %0
diff --git a/gcc/config/cr16/cr16.c b/gcc/config/cr16/cr16.c
index 0dc9435078d..fbc2b5cf67a 100644
--- a/gcc/config/cr16/cr16.c
+++ b/gcc/config/cr16/cr16.c
@@ -2109,14 +2109,14 @@ notice_update_cc (rtx exp)
          the RTX's which we remember the cc's came from.
          (Note that moving a constant 0 or 1 MAY set the cc's).  */
       if (REG_P (SET_DEST (exp))
-	  && (REG_P (SET_SRC (exp)) || GET_CODE (SET_SRC (exp)) == MEM))
+	  && (REG_P (SET_SRC (exp)) || MEM_P (SET_SRC (exp))))
 	{
 	  return;
 	}
 
       /* Moving register into memory doesn't alter the cc's.
          It may invalidate the RTX's which we remember the cc's came from.  */
-      if (GET_CODE (SET_DEST (exp)) == MEM && REG_P (SET_SRC (exp)))
+      if (MEM_P (SET_DEST (exp)) && REG_P (SET_SRC (exp)))
 	{
 	  return;
 	}
diff --git a/gcc/config/cr16/cr16.h b/gcc/config/cr16/cr16.h
index 227b536d1c9..dbc012a197d 100644
--- a/gcc/config/cr16/cr16.h
+++ b/gcc/config/cr16/cr16.h
@@ -340,9 +340,9 @@ enum reg_class
 
 /* This check is for sbit/cbit instruction.  */
 #define OK_FOR_Z(OP) \
-  ((GET_CODE (OP) == MEM && CONST_INT_P (XEXP (OP, 0))) \
-   || (GET_CODE (OP) == MEM && REG_P (XEXP (OP, 0))) \
-   || (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == PLUS \
+  ((MEM_P (OP) && CONST_INT_P (XEXP (OP, 0))) \
+   || (MEM_P (OP) && REG_P (XEXP (OP, 0))) \
+   || (MEM_P (OP) && GET_CODE (XEXP (OP, 0)) == PLUS \
        && REG_P (XEXP ((XEXP (OP, 0)), 0)) \
        && CONST_INT_P (XEXP ((XEXP (OP, 0)), 1))))
 
diff --git a/gcc/config/cr16/predicates.md b/gcc/config/cr16/predicates.md
index b1e3193889f..5800123c558 100644
--- a/gcc/config/cr16/predicates.md
+++ b/gcc/config/cr16/predicates.md
@@ -25,7 +25,7 @@
 (define_predicate "bit_operand"
   (match_code "mem")
 {
-  return ((GET_CODE (op) == MEM && OK_FOR_Z (op)));
+  return ((MEM_P (op) && OK_FOR_Z (op)));
 })
 
 ;; Unsigned 4-bits constant int or double value.
diff --git a/gcc/config/csky/csky.c b/gcc/config/csky/csky.c
index fd2291f176c..2cd0630ac88 100644
--- a/gcc/config/csky/csky.c
+++ b/gcc/config/csky/csky.c
@@ -1408,7 +1408,7 @@ csky_minipool_load_p (rtx_insn *insn)
   /* Constant pool loads are label_refs.  */
   if (GET_CODE (op1) == ZERO_EXTEND || GET_CODE (op1) == SIGN_EXTEND)
     op1 = XEXP (op1, 0);
-  if (GET_CODE (op1) != MEM)
+  if (!MEM_P (op1))
     return false;
   addr = XEXP (op1, 0);
   if (GET_CODE (addr) == PLUS && CONST_INT_P (XEXP (addr, 1)))
@@ -3966,7 +3966,7 @@ csky_output_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
 	      return "mov\t%0, %1";
 	}
       /* The situation mov memory to reg.  */
-      else if (GET_CODE (src) == MEM)
+      else if (MEM_P (src))
 	{
 	  decompose_csky_address (XEXP (src, 0), &op1);
 
@@ -4048,7 +4048,7 @@ csky_output_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
       else
 	return "lrw\t%0, %1";
     }
-  else if (GET_CODE (dst) == MEM)
+  else if (MEM_P (dst))
     {
       decompose_csky_address (XEXP (dst, 0), &op0);
 
@@ -4104,7 +4104,7 @@ csky_output_ck801_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
     {
       if (REG_P (src))
 	return "mov\t%0, %1";
-      else if (GET_CODE (src) == MEM)
+      else if (MEM_P (src))
 	{
 	  decompose_csky_address (XEXP (src, 0), &op1);
 
@@ -4166,7 +4166,7 @@ csky_output_ck801_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
       else
 	return "lrw\t%0, %1";
     }
-  else if (GET_CODE (dst) == MEM)
+  else if (MEM_P (dst))
     switch (GET_MODE (dst))
       {
       case E_HImode:
@@ -4246,7 +4246,7 @@ csky_output_movedouble (rtx operands[],
 	  else
 	    return "mov\t%0, %1\n\tmov\t%R0, %R1";
 	}
-      else if (GET_CODE (src) == MEM)
+      else if (MEM_P (src))
 	{
 	  rtx memexp = XEXP (src, 0);
 	  int dstreg = REGNO (dst);
@@ -4318,7 +4318,7 @@ csky_output_movedouble (rtx operands[],
       else
 	gcc_unreachable ();
     }
-  else if (GET_CODE (dst) == MEM && REG_P (src))
+  else if (MEM_P (dst) && REG_P (src))
     {
       rtx memexp = XEXP (dst, 0);
       int srcreg = REGNO (src);
@@ -4381,7 +4381,7 @@ csky_output_ck801_movedouble (rtx operands[],
 	  else
 	    return "mov\t%0, %1\n\tmov\t%R0, %R1";
 	}
-      else if (GET_CODE (src) == MEM)
+      else if (MEM_P (src))
 	{
 	  rtx memexp = XEXP (src, 0);
 	  int dstreg = REGNO (dst);
@@ -4440,7 +4440,7 @@ csky_output_ck801_movedouble (rtx operands[],
       else
 	gcc_unreachable ();
     }
-  else if (GET_CODE (dst) == MEM && REG_P (src))
+  else if (MEM_P (dst) && REG_P (src))
     {
       rtx memexp = XEXP (dst, 0);
       int srcreg = REGNO (src);
@@ -5942,7 +5942,7 @@ csky_valid_fpuv2_mem_operand (rtx op)
 {
   struct csky_address addr;
 
-  if (GET_CODE (op) != MEM)
+  if (!MEM_P (op))
     return false;
 
   if (!decompose_csky_address (XEXP (op, 0), &addr))
@@ -6523,7 +6523,7 @@ csky_sched_adjust_cost (rtx_insn *insn,
 	      enum rtx_code code = GET_CODE (addr);
 	      if (code == ZERO_EXTEND || code == SIGN_EXTEND)
 		addr = XEXP (addr, 0);
-	      gcc_assert (GET_CODE (addr) == MEM);
+	      gcc_assert (MEM_P (addr));
 
 	      rtx base =  XEXP (addr, 0);
 	      rtx reg = NULL_RTX;
@@ -6554,7 +6554,7 @@ csky_sched_adjust_cost (rtx_insn *insn,
 	      enum rtx_code code = GET_CODE (addr);
 	      if (code == ZERO_EXTEND || code == SIGN_EXTEND)
 		addr = XEXP (addr, 0);
-	      gcc_assert (GET_CODE (addr) == MEM);
+	      gcc_assert (MEM_P (addr));
 
 	      rtx base =  XEXP (addr, 0);
 	      rtx reg = NULL_RTX;
diff --git a/gcc/config/csky/csky.md b/gcc/config/csky/csky.md
index 2dd1452eb3b..6e680c14ac2 100644
--- a/gcc/config/csky/csky.md
+++ b/gcc/config/csky/csky.md
@@ -259,7 +259,7 @@
   ""
   "
   {
-    if (GET_CODE (operands[0]) == MEM)
+    if (MEM_P (operands[0]))
 	operands[1] = force_reg (HImode, operands[1]);
     else if (CONSTANT_P (operands[1])
 	     && (!CONST_INT_P (operands[1])
@@ -300,7 +300,7 @@
   ""
   "
   {
-    if (can_create_pseudo_p () && GET_CODE (operands[0]) == MEM)
+    if (can_create_pseudo_p () && MEM_P (operands[0]))
 	operands[1] = force_reg (QImode, operands[1]);
     else if (CONSTANT_P (operands[1])
 	     && (!CONST_INT_P (operands[1])
@@ -339,7 +339,7 @@
   [(set (match_operand:DI 0 "general_operand" "")
 	(match_operand:DI 1 "general_operand" ""))]
   ""
-  "if (can_create_pseudo_p () && GET_CODE (operands[0]) == MEM)
+  "if (can_create_pseudo_p () && MEM_P (operands[0]))
       operands[1] = force_reg (DImode, operands[1]);"
 )
 
@@ -428,7 +428,7 @@
 	(match_operand:SF 1 "general_operand" ""))]
   ""
   "
-  if (GET_CODE (operands[0]) == MEM && can_create_pseudo_p ())
+  if (MEM_P (operands[0]) && can_create_pseudo_p ())
     operands[1] = force_reg (SFmode, operands[1]);
   "
 )
@@ -467,7 +467,7 @@
 	(match_operand:DF 1 "general_operand" ""))]
   ""
   "
-  if (GET_CODE (operands[0]) == MEM && can_create_pseudo_p ())
+  if (MEM_P (operands[0]) && can_create_pseudo_p ())
       operands[1] = force_reg (DFmode, operands[1]);
   "
 )
@@ -2057,7 +2057,7 @@
     if (!CONST_INT_P (operands[2])
 	|| INTVAL (operands[2]) < 2
 	|| INTVAL (operands[2]) > CSKY_MAX_MULTIPLE_STLD
-	|| GET_CODE (operands[1]) != MEM
+	|| !MEM_P (operands[1])
 	|| !REG_P (XEXP (operands[1], 0))
 	|| XEXP (operands[1], 0) != stack_pointer_rtx
 	|| !REG_P (operands[0])
@@ -2095,7 +2095,7 @@
     if (!CONST_INT_P (operands[2])
 	|| INTVAL (operands[2]) < 2
 	|| INTVAL (operands[2]) > CSKY_MAX_MULTIPLE_STLD
-	|| GET_CODE (operands[0]) != MEM
+	|| !MEM_P (operands[0])
 	|| !REG_P (XEXP (operands[0], 0))
 	|| XEXP (operands[0], 0) != stack_pointer_rtx
 	|| !REG_P (operands[1])
@@ -3250,7 +3250,7 @@
 	operands[0] = gen_rtx_MEM (GET_MODE (pic_ref), pic_ref);
       }
 
-     if (GET_CODE (operands[0]) == MEM
+     if (MEM_P (operands[0])
 	 && ! register_operand (XEXP (operands[0], 0), SImode)
 	 && ! csky_symbolic_address_p (XEXP (operands[0], 0))
 	 && ! (flag_pic
@@ -3301,7 +3301,7 @@
 	operands[1] = gen_rtx_MEM (GET_MODE (pic_ref), pic_ref);
       }
 
-     if (GET_CODE (operands[1]) == MEM
+     if (MEM_P (operands[1])
 	 && ! register_operand (XEXP (operands[1], 0), SImode)
 	 && ! csky_symbolic_address_p (XEXP (operands[1], 0))
 	 && ! (flag_pic
diff --git a/gcc/config/csky/predicates.md b/gcc/config/csky/predicates.md
index 93725f15209..c2dadba3d27 100644
--- a/gcc/config/csky/predicates.md
+++ b/gcc/config/csky/predicates.md
@@ -32,7 +32,7 @@
   if (count <= 1
       || GET_CODE (XVECEXP (op, 0, 0)) != SET
       || !REG_P (SET_DEST (XVECEXP (op, 0, 0)))
-      || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM
+      || !MEM_P (SET_SRC (XVECEXP (op, 0, 0)))
       || !REG_P (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0))
       || XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0) != stack_pointer_rtx)
     return 0;
@@ -48,7 +48,7 @@
 	  || !REG_P (SET_DEST (elt))
 	  || GET_MODE (SET_DEST (elt)) != SImode
 	  || REGNO (SET_DEST (elt)) != (unsigned) (dest_regno + i)
-	  || GET_CODE (SET_SRC (elt)) != MEM
+	  || !MEM_P (SET_SRC (elt))
 	  || GET_MODE (SET_SRC (elt)) != SImode
 	  || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
 	  || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
@@ -72,7 +72,7 @@
   /* Perform a quick check so we don't blow up below.  */
   if (count <= 1
       || GET_CODE (XVECEXP (op, 0, 0)) != SET
-      || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
+      || !MEM_P (SET_DEST (XVECEXP (op, 0, 0)))
       || !REG_P (XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0))
       || XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0) != stack_pointer_rtx
       || !REG_P (SET_SRC (XVECEXP (op, 0, 0))))
@@ -89,7 +89,7 @@
 	  || !REG_P (SET_SRC (elt))
 	  || GET_MODE (SET_SRC (elt)) != SImode
 	  || REGNO (SET_SRC (elt)) != (unsigned) (src_regno + i)
-	  || GET_CODE (SET_DEST (elt)) != MEM
+	  || !MEM_P (SET_DEST (elt))
 	  || GET_MODE (SET_DEST (elt)) != SImode
 	  || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
 	  || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
diff --git a/gcc/config/darwin.c b/gcc/config/darwin.c
index 8dea5b9f33c..ef6e27ff34c 100644
--- a/gcc/config/darwin.c
+++ b/gcc/config/darwin.c
@@ -347,7 +347,7 @@ machopic_define_symbol (rtx mem)
 {
   rtx sym_ref;
 
-  gcc_assert (GET_CODE (mem) == MEM);
+  gcc_assert (MEM_P (mem));
   sym_ref = XEXP (mem, 0);
   SYMBOL_REF_FLAGS (sym_ref) |= MACHO_SYMBOL_FLAG_DEFINED;
 }
@@ -730,7 +730,7 @@ machopic_indirect_data_reference (rtx orig, rtx reg)
       else
 	return orig;
     }
-  else if (GET_CODE (orig) == MEM)
+  else if (MEM_P (orig))
     {
       XEXP (ptr_ref, 0) =
 		machopic_indirect_data_reference (XEXP (orig, 0), reg);
@@ -764,7 +764,7 @@ machopic_indirect_data_reference (rtx orig, rtx reg)
       else
 	result = gen_rtx_PLUS (Pmode, base, orig);
 
-      if (MACHOPIC_JUST_INDIRECT && GET_CODE (base) == MEM)
+      if (MACHOPIC_JUST_INDIRECT && MEM_P (base))
 	{
 	  if (reg)
 	    {
@@ -791,7 +791,7 @@ machopic_indirect_call_target (rtx target)
   if (! darwin_picsymbol_stubs)
     return target;
 
-  if (GET_CODE (target) != MEM)
+  if (!MEM_P (target))
     return target;
 
   if (MACHOPIC_INDIRECT
@@ -838,7 +838,7 @@ machopic_legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
 	  return reg;
 	}
 
-      if (GET_CODE (orig) == MEM)
+      if (MEM_P (orig))
 	{
 	  if (reg == 0)
 	    {
@@ -1023,7 +1023,7 @@ machopic_legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
         }
     }
   else if (GET_CODE (orig) == PLUS
-	   && (GET_CODE (XEXP (orig, 0)) == MEM
+	   && (MEM_P (XEXP (orig, 0))
 	       || GET_CODE (XEXP (orig, 0)) == SYMBOL_REF
 	       || GET_CODE (XEXP (orig, 0)) == LABEL_REF)
 	   && XEXP (orig, 0) != pic_offset_table_rtx
@@ -1031,7 +1031,7 @@ machopic_legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
 
     {
       rtx base;
-      int is_complex = (GET_CODE (XEXP (orig, 0)) == MEM);
+      int is_complex = (MEM_P (XEXP (orig, 0)));
 
       base = machopic_legitimize_pic_address (XEXP (orig, 0), Pmode, reg);
       orig = machopic_legitimize_pic_address (XEXP (orig, 1),
@@ -1055,7 +1055,7 @@ machopic_legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
     {
       return machopic_legitimize_pic_address (XEXP (orig, 0), Pmode, reg);
     }
-  else if (GET_CODE (orig) == MEM
+  else if (MEM_P (orig)
 	   && GET_CODE (XEXP (orig, 0)) == SYMBOL_REF)
     {
       rtx addr = machopic_legitimize_pic_address (XEXP (orig, 0), Pmode, reg);
diff --git a/gcc/config/epiphany/epiphany.md b/gcc/config/epiphany/epiphany.md
index 354a21f5c41..83b8e76062e 100644
--- a/gcc/config/epiphany/epiphany.md
+++ b/gcc/config/epiphany/epiphany.md
@@ -121,7 +121,7 @@
       emit_insn (gen_movsi (operands[0], operands[1]));
       DONE;
     }
-  if (GET_CODE (operands[0]) == MEM)
+  if (MEM_P (operands[0]))
     operands[1] = force_reg (<MODE>mode, operands[1]);
   if (<MODE>mode == SImode
       && (operands[1] == frame_pointer_rtx || operands[1] == arg_pointer_rtx))
@@ -333,7 +333,7 @@
 	 subregs.  */
       if (epiphany_vect_align != 4 /* == 8 */
 	  && !reload_in_progress
-	  && (GET_CODE (operands[0]) == MEM || GET_CODE (operands[1]) == MEM)
+	  && (MEM_P (operands[0]) || MEM_P (operands[1]))
 	  && !misaligned_operand (operands[1], <MODE>mode)
 	  && (!SUBREG_P (operands[0])
 	      || (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0])))
@@ -350,7 +350,7 @@
     }
   /* Everything except mem = const or mem = mem can be done easily.  */
 
-  if (GET_CODE (operands[0]) == MEM)
+  if (MEM_P (operands[0]))
     operands[1] = force_reg (<MODE>mode, operands[1]);
 }")
 
diff --git a/gcc/config/epiphany/predicates.md b/gcc/config/epiphany/predicates.md
index 1d881a22d50..07b44b5ec65 100644
--- a/gcc/config/epiphany/predicates.md
+++ b/gcc/config/epiphany/predicates.md
@@ -144,7 +144,7 @@
     case SUBREG :
       /* (subreg (mem ...) ...) can occur here if the inner part was once a
 	 pseudo-reg and is now a stack slot.  */
-      if (GET_CODE (SUBREG_REG (op)) == MEM)
+      if (MEM_P (SUBREG_REG (op)))
 	return address_operand (XEXP (SUBREG_REG (op), 0), mode);
       else
 	return register_operand (op, mode);
@@ -162,7 +162,7 @@
 (define_predicate "move_double_src_operand"
   (match_code "reg,subreg,mem,const_int,const_double,const_vector")
 {
-  if (GET_CODE (op) == MEM && misaligned_operand (op, mode)
+  if (MEM_P (op) && misaligned_operand (op, mode)
       && !address_operand (plus_constant (Pmode, XEXP (op, 0), 4), SImode))
     return 0;
   return general_operand (op, mode);
@@ -180,7 +180,7 @@
     case SUBREG :
       /* (subreg (mem ...) ...) can occur here if the inner part was once a
 	 pseudo-reg and is now a stack slot.  */
-      if (GET_CODE (SUBREG_REG (op)) == MEM)
+      if (MEM_P (SUBREG_REG (op)))
 	{
 	  return address_operand (XEXP (SUBREG_REG (op), 0), mode);
 	}
diff --git a/gcc/config/fr30/fr30.md b/gcc/config/fr30/fr30.md
index f19dbdabd81..3413eaaedc5 100644
--- a/gcc/config/fr30/fr30.md
+++ b/gcc/config/fr30/fr30.md
@@ -166,8 +166,8 @@
 {
   if (!reload_in_progress
       && !reload_completed
-      && GET_CODE (operands[0]) == MEM
-      && (GET_CODE (operands[1]) == MEM
+      && MEM_P (operands[0])
+      && (MEM_P (operands[1])
          || immediate_operand (operands[1], QImode)))
     operands[1] = copy_to_mode_reg (QImode, operands[1]);
 }")
@@ -212,8 +212,8 @@
 {
   if (!reload_in_progress
       && !reload_completed
-      && GET_CODE (operands[0]) == MEM
-      && (GET_CODE (operands[1]) == MEM
+      && MEM_P (operands[0])
+      && (MEM_P (operands[1])
 	 || immediate_operand (operands[1], HImode)))
     operands[1] = copy_to_mode_reg (HImode, operands[1]);
 }")
@@ -262,8 +262,8 @@
   "{
   if (!reload_in_progress
       && !reload_completed
-      && GET_CODE(operands[0]) == MEM
-      && (GET_CODE (operands[1]) == MEM
+      && MEM_P (operands[0])
+      && (MEM_P (operands[1])
 	  || immediate_operand (operands[1], SImode)))
      operands[1] = copy_to_mode_reg (SImode, operands[1]);
   }"
@@ -386,7 +386,7 @@
   "
   /* Everything except mem = const or mem = mem can be done easily.  */
 
-  if (GET_CODE (operands[0]) == MEM)
+  if (MEM_P (operands[0]))
     operands[1] = force_reg (DImode, operands[1]);
   "
 )
diff --git a/gcc/config/fr30/predicates.md b/gcc/config/fr30/predicates.md
index 330a74523a5..1fa5f167f27 100644
--- a/gcc/config/fr30/predicates.md
+++ b/gcc/config/fr30/predicates.md
@@ -56,7 +56,7 @@
 (define_predicate "call_operand"
   (match_code "mem")
 {
-  return (GET_CODE (op) == MEM
+  return (MEM_P (op)
 	  && (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
 	      || REG_P (XEXP (op, 0))));
 })
@@ -103,7 +103,7 @@
   if (SUBREG_P (op))
     op = SUBREG_REG (op);
 
-  if (GET_CODE (op) == MEM)
+  if (MEM_P (op))
     return memory_address_p (DImode, XEXP (op, 0));
 
   return FALSE;
diff --git a/gcc/config/frv/frv.c b/gcc/config/frv/frv.c
index a1df8153a22..e16508dba44 100644
--- a/gcc/config/frv/frv.c
+++ b/gcc/config/frv/frv.c
@@ -2466,7 +2466,7 @@ frv_index_memory (rtx memref, machine_mode mode, int index)
 static void
 frv_print_operand_address (FILE * stream, machine_mode /* mode */, rtx x)
 {
-  if (GET_CODE (x) == MEM)
+  if (MEM_P (x))
     x = XEXP (x, 0);
 
   switch (GET_CODE (x))
@@ -2858,7 +2858,7 @@ frv_print_operand (FILE * file, rtx x, int code)
     case 'I':
       /* Print 'i' if the operand is a constant, or is a memory reference that
          adds a constant.  */
-      if (GET_CODE (x) == MEM)
+      if (MEM_P (x))
 	x = ((GET_CODE (XEXP (x, 0)) == PLUS)
 	     ? XEXP (XEXP (x, 0), 1)
 	     : XEXP (x, 0));
@@ -2958,7 +2958,7 @@ frv_print_operand (FILE * file, rtx x, int code)
 
     case 'U':
       /* Print 'u' if the operand is a update load/store.  */
-      if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
+      if (MEM_P (x) && GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
 	fputs ("u", file);
       break;
 
@@ -2995,7 +2995,7 @@ frv_print_operand (FILE * file, rtx x, int code)
       else if (frv_const_unspec_p (x, &unspec))
 	frv_output_const_unspec (file, &unspec);
 
-      else if (GET_CODE (x) == MEM)
+      else if (MEM_P (x))
         frv_print_operand_address (file, GET_MODE (x), XEXP (x, 0));
 
       else if (CONSTANT_ADDRESS_P (x))
@@ -3733,7 +3733,7 @@ int
 frv_legitimate_memory_operand (rtx op, machine_mode mode, int condexec_p)
 {
   return ((GET_MODE (op) == mode || mode == VOIDmode)
-	  && GET_CODE (op) == MEM
+	  && MEM_P (op)
 	  && frv_legitimate_address_p_1 (mode, XEXP (op, 0),
 				         reload_completed, condexec_p, FALSE));
 }
@@ -3891,7 +3891,7 @@ condexec_memory_operand (rtx op, machine_mode mode)
       break;
     }
 
-  if (GET_CODE (op) != MEM)
+  if (!MEM_P (op))
     return FALSE;
 
   addr = XEXP (op, 0);
@@ -4232,7 +4232,7 @@ output_move_single (rtx operands[], rtx insn)
 		return "movsg %1, %0";
 	    }
 
-	  else if (GET_CODE (src) == MEM)
+	  else if (MEM_P (src))
 	    {
 	      /* gpr <- memory */
 	      switch (mode)
@@ -4306,7 +4306,7 @@ output_move_single (rtx operands[], rtx insn)
 		}
 	    }
 
-	  else if (GET_CODE (src) == MEM)
+	  else if (MEM_P (src))
 	    {
 	      /* fpr <- memory */
 	      switch (mode)
@@ -4345,7 +4345,7 @@ output_move_single (rtx operands[], rtx insn)
 	}
     }
 
-  else if (GET_CODE (dest) == MEM)
+  else if (MEM_P (dest))
     {
       if (REG_P (src))
 	{
@@ -4449,7 +4449,7 @@ output_move_double (rtx operands[], rtx insn)
 		}
 	    }
 
-	  else if (GET_CODE (src) == MEM)
+	  else if (MEM_P (src))
 	    {
 	      /* gpr <- memory */
 	      if (dbl_memory_one_insn_operand (src, mode))
@@ -4490,7 +4490,7 @@ output_move_double (rtx operands[], rtx insn)
 		}
 	    }
 
-	  else if (GET_CODE (src) == MEM)
+	  else if (MEM_P (src))
 	    {
 	      /* fpr <- memory */
 	      if (dbl_memory_one_insn_operand (src, mode))
@@ -4504,7 +4504,7 @@ output_move_double (rtx operands[], rtx insn)
 	}
     }
 
-  else if (GET_CODE (dest) == MEM)
+  else if (MEM_P (dest))
     {
       if (REG_P (src))
 	{
@@ -4574,7 +4574,7 @@ output_condmove_single (rtx operands[], rtx insn)
 		return "cmovfg %3, %2, %1, %e0";
 	    }
 
-	  else if (GET_CODE (src) == MEM)
+	  else if (MEM_P (src))
 	    {
 	      /* gpr <- memory */
 	      switch (mode)
@@ -4617,7 +4617,7 @@ output_condmove_single (rtx operands[], rtx insn)
 		}
 	    }
 
-	  else if (GET_CODE (src) == MEM)
+	  else if (MEM_P (src))
 	    {
 	      /* fpr <- memory */
 	      if (mode == SImode || mode == SFmode)
@@ -4629,7 +4629,7 @@ output_condmove_single (rtx operands[], rtx insn)
 	}
     }
 
-  else if (GET_CODE (dest) == MEM)
+  else if (MEM_P (dest))
     {
       if (REG_P (src))
 	{
@@ -6002,7 +6002,7 @@ frv_ifcvt_modify_insn (ce_if_block *ce_info,
 	    }
 
 	  /* See if we need to fix up stores */
-	  if (GET_CODE (dest) == MEM)
+	  if (MEM_P (dest))
 	    {
 	      rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn);
 
@@ -6017,7 +6017,7 @@ frv_ifcvt_modify_insn (ce_if_block *ce_info,
 	    }
 
 	  /* See if we need to fix up loads */
-	  if (GET_CODE (src) == MEM)
+	  if (MEM_P (src))
 	    {
 	      rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn);
 
@@ -7081,7 +7081,7 @@ frv_registers_conflict_p_1 (rtx pat, regstate_t cond)
 	      if (frv_regstate_conflict_p (frv_packet.regstate[regno], cond))
 		return true;
 	}
-      else if (GET_CODE (x) == MEM)
+      else if (MEM_P (x))
 	{
 	  /* If we ran out of memory slots, assume a conflict.  */
 	  if (frv_packet.num_mems > ARRAY_SIZE (frv_packet.mems))
@@ -7141,7 +7141,7 @@ frv_registers_update_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
     FOR_EACH_REGNO (regno, x)
       frv_packet.regstate[regno] |= *(regstate_t *) data;
 
-  if (GET_CODE (x) == MEM)
+  if (MEM_P (x))
     {
       if (frv_packet.num_mems < ARRAY_SIZE (frv_packet.mems))
 	{
@@ -7822,7 +7822,7 @@ frv_optimize_membar_local (basic_block bb, struct frv_io *next_io,
 	      if (GET_CODE (src) == ZERO_EXTEND)
 		src = XEXP (src, 0);
 
-	      if (GET_CODE (src) == MEM
+	      if (MEM_P (src)
 		  && rtx_equal_p (XEXP (src, 0), next_io->var_address))
 		{
 		  if (dump_file)
@@ -8815,7 +8815,7 @@ frv_expand_voidbinop_builtin (enum insn_code icode, tree call)
   machine_mode mode0 = insn_data[icode].operand[0].mode;
   rtx addr;
 
-  if (GET_CODE (op0) != MEM)
+  if (!MEM_P (op0))
     {
       rtx reg = op0;
 
diff --git a/gcc/config/frv/frv.md b/gcc/config/frv/frv.md
index d365476ef0a..cac99227522 100644
--- a/gcc/config/frv/frv.md
+++ b/gcc/config/frv/frv.md
@@ -2185,7 +2185,7 @@
       rtx addr;
       rtx temp3 = simplify_gen_subreg (SImode, operands[2], TImode, 12);
 
-      gcc_assert (GET_CODE (operands[1]) == MEM);
+      gcc_assert (MEM_P (operands[1]));
 
       addr = XEXP (operands[1], 0);
 
@@ -4874,7 +4874,7 @@
   rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
   rtx addr;
 
-  gcc_assert (GET_CODE (operands[0]) == MEM);
+  gcc_assert (MEM_P (operands[0]));
 
   addr = XEXP (operands[0], 0);
   if (! call_operand (addr, Pmode))
@@ -4959,7 +4959,7 @@
 {
   rtx addr;
 
-  gcc_assert (GET_CODE (operands[0]) == MEM);
+  gcc_assert (MEM_P (operands[0]));
 
   addr = XEXP (operands[0], 0);
   if (! sibcall_operand (addr, Pmode))
@@ -5026,7 +5026,7 @@
   rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
   rtx addr;
 
-  gcc_assert (GET_CODE (operands[1]) == MEM);
+  gcc_assert (MEM_P (operands[1]));
 
   addr = XEXP (operands[1], 0);
   if (! call_operand (addr, Pmode))
@@ -5092,7 +5092,7 @@
 {
   rtx addr;
 
-  gcc_assert (GET_CODE (operands[1]) == MEM);
+  gcc_assert (MEM_P (operands[1]));
 
   addr = XEXP (operands[1], 0);
   if (! sibcall_operand (addr, Pmode))
diff --git a/gcc/config/frv/predicates.md b/gcc/config/frv/predicates.md
index bbe55939a62..fb4f13b32e6 100644
--- a/gcc/config/frv/predicates.md
+++ b/gcc/config/frv/predicates.md
@@ -455,7 +455,7 @@
   if (gpr_or_memory_operand (op, mode))
     return TRUE;
 
-  if (GET_CODE (op) != MEM)
+  if (!MEM_P (op))
     return FALSE;
 
   if (GET_MODE (op) != mode)
@@ -1004,7 +1004,7 @@
   if (! TARGET_DWORD)
     return FALSE;
 
-  if (GET_CODE (op) != MEM)
+  if (!MEM_P (op))
     return FALSE;
 
   if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD)
@@ -1049,7 +1049,7 @@
 (define_predicate "dbl_memory_two_insn_operand"
   (match_code "mem")
 {
-  if (GET_CODE (op) != MEM)
+  if (!MEM_P (op))
     return FALSE;
 
   if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD)
diff --git a/gcc/config/h8300/h8300.c b/gcc/config/h8300/h8300.c
index 5e1fe1b682b..d9d69e4791e 100644
--- a/gcc/config/h8300/h8300.c
+++ b/gcc/config/h8300/h8300.c
@@ -756,7 +756,7 @@ h8300_ldm_stm_regno (rtx x, int load_p, int index, int nregs)
 
   if (GET_CODE (x) == SET
       && REG_P (XEXP (x, regindex))
-      && GET_CODE (XEXP (x, memindex)) == MEM
+      && MEM_P (XEXP (x, memindex))
       && h8300_stack_offset_p (XEXP (XEXP (x, memindex), 0), offset))
     return REGNO (XEXP (x, regindex));
 
@@ -2324,7 +2324,7 @@ h8300_classify_operand (rtx op, int size, enum h8300_operand_class *opclass)
 
       return size;
     }
-  else if (GET_CODE (op) == MEM)
+  else if (MEM_P (op))
     {
       op = XEXP (op, 0);
       if (CONSTANT_P (op))
@@ -2484,7 +2484,7 @@ h8300_short_move_mem_p (rtx op, enum rtx_code inc_code)
   rtx addr;
   unsigned int size;
 
-  if (GET_CODE (op) != MEM)
+  if (!MEM_P (op))
     return false;
 
   addr = XEXP (op, 0);
@@ -2611,7 +2611,7 @@ h8300_insn_length_from_table (rtx_insn *insn, rtx * operands)
 bool
 h8sx_mergeable_memrefs_p (rtx lhs, rtx rhs)
 {
-  if (GET_CODE (rhs) == MEM && GET_CODE (lhs) == MEM)
+  if (MEM_P (rhs) && MEM_P (lhs))
     {
       rhs = XEXP (rhs, 0);
       lhs = XEXP (lhs, 0);
@@ -2797,9 +2797,9 @@ compute_mov_length (rtx *operands)
   rtx src = operands[1];
   rtx addr;
 
-  if (GET_CODE (src) == MEM)
+  if (MEM_P (src))
     addr = XEXP (src, 0);
-  else if (GET_CODE (dest) == MEM)
+  else if (MEM_P (dest))
     addr = XEXP (dest, 0);
   else
     addr = NULL_RTX;
@@ -5228,7 +5228,7 @@ fix_bit_operand (rtx *operands, enum rtx_code code)
       : single_one_operand (operands[2], QImode))
     {
       /* OK to have a memory dest.  */
-      if (GET_CODE (operands[0]) == MEM
+      if (MEM_P (operands[0])
 	  && !satisfies_constraint_U (operands[0]))
 	{
 	  rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
@@ -5238,7 +5238,7 @@ fix_bit_operand (rtx *operands, enum rtx_code code)
 	  operands[0] = mem;
 	}
 
-      if (GET_CODE (operands[1]) == MEM
+      if (MEM_P (operands[1])
 	  && !satisfies_constraint_U (operands[1]))
 	{
 	  rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md
index 082ef9a7f74..401420c42f1 100644
--- a/gcc/config/h8300/h8300.md
+++ b/gcc/config/h8300/h8300.md
@@ -327,7 +327,7 @@
 	return "mov.w	%f1,%f0\;mov.w	%e1,%e0";
     case 2:
       /* Make sure we don't trample the register we index with.  */
-      if (GET_CODE (operands[1]) == MEM)
+      if (MEM_P (operands[1]))
 	{
 	  rtx inside = XEXP (operands[1], 0);
 	  if (REG_P (inside))
@@ -662,7 +662,7 @@
 	return "mov.w	%f1,%f0\;mov.w	%e1,%e0";
     case 2:
       /* Make sure we don't trample the register we index with.  */
-      if (GET_CODE (operands[1]) == MEM)
+      if (MEM_P (operands[1]))
 	{
 	  rtx inside = XEXP (operands[1], 0);
 	  if (REG_P (inside))
@@ -2990,8 +2990,8 @@
       FAIL;
 
     /* For now, we don't allow memory operands.  */
-    if (GET_CODE (operands[0]) == MEM
-	|| GET_CODE (operands[3]) == MEM)
+    if (MEM_P (operands[0])
+	|| MEM_P (operands[3]))
       FAIL;
 
     if (!REG_P (operands[3]))
@@ -3060,7 +3060,7 @@
       FAIL;
 
     /* For now, we don't allow memory operands.  */
-    if (GET_CODE (operands[1]) == MEM)
+    if (MEM_P (operands[1]))
       FAIL;
   })
 
@@ -4654,8 +4654,8 @@
 		(const_int 255)))]
   "(TARGET_H8300H || TARGET_H8300S)
     && !reg_overlap_mentioned_p (operands[0], operands[1])
-    && !(GET_CODE (operands[1]) == MEM && !offsettable_memref_p (operands[1]))
-    && !(GET_CODE (operands[1]) == MEM && MEM_VOLATILE_P (operands[1]))"
+    && !(MEM_P (operands[1]) && !offsettable_memref_p (operands[1]))
+    && !(MEM_P (operands[1]) && MEM_VOLATILE_P (operands[1]))"
   [(set (match_dup 0)
 	(const_int 0))
    (set (strict_low_part (match_dup 2))
@@ -4679,10 +4679,10 @@
     && REGNO (operands[0]) == REGNO (operands[2])
     && !reg_overlap_mentioned_p (operands[2], operands[1])
     && !(GET_MODE (operands[1]) != QImode
-	 && GET_CODE (operands[1]) == MEM
+	 && MEM_P (operands[1])
 	 && !offsettable_memref_p (operands[1]))
     && !(GET_MODE (operands[1]) != QImode
-	 && GET_CODE (operands[1]) == MEM
+	 && MEM_P (operands[1])
 	 && MEM_VOLATILE_P (operands[1]))"
   [(set (match_dup 2)
 	(const_int 0))
diff --git a/gcc/config/h8300/predicates.md b/gcc/config/h8300/predicates.md
index 4eeb34bb75d..b71bdde6de8 100644
--- a/gcc/config/h8300/predicates.md
+++ b/gcc/config/h8300/predicates.md
@@ -24,7 +24,7 @@
   (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem")
 {
   if (GET_MODE (op) == mode
-      && GET_CODE (op) == MEM
+      && MEM_P (op)
       && GET_CODE (XEXP (op, 0)) == POST_INC)
     return 1;
   return general_operand (op, mode);
@@ -37,7 +37,7 @@
   (match_code "subreg,reg,mem")
 {
   if (GET_MODE (op) == mode
-      && GET_CODE (op) == MEM
+      && MEM_P (op)
       && GET_CODE (XEXP (op, 0)) == PRE_DEC)
     return 1;
   return general_operand (op, mode);
@@ -219,7 +219,7 @@
 (define_predicate "call_expander_operand"
   (match_code "mem")
 {
-  if (GET_CODE (op) == MEM)
+  if (MEM_P (op))
     {
       rtx inside = XEXP (op, 0);
       if (register_operand (inside, Pmode))
@@ -267,7 +267,7 @@
   if (REG_P (op))
     return GET_MODE (op) == Pmode;
 
-  if (GET_CODE (op) == MEM)
+  if (MEM_P (op))
     {
       rtx inside = XEXP (op, 0);
       if (register_operand (inside, Pmode))
@@ -349,7 +349,7 @@
     return 1;
   if (SUBREG_P (op))
     return 1;
-  return (GET_CODE (op) == MEM
+  return (MEM_P (op)
 	  && satisfies_constraint_U (op));
 })
 
@@ -358,7 +358,7 @@
 (define_predicate "bit_memory_operand"
   (match_code "mem")
 {
-  return (GET_CODE (op) == MEM
+  return (MEM_P (op)
 	  && satisfies_constraint_U (op));
 })
 
@@ -368,7 +368,7 @@
 (define_predicate "bit_register_indirect_operand"
   (match_code "mem")
 {
-  return (GET_CODE (op) == MEM
+  return (MEM_P (op)
           && (REG_P (XEXP (op, 0))
               || CONST_INT_P (XEXP (op, 0))));
 })
diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c
index f6ab07de01b..e83ab66a598 100644
--- a/gcc/config/i386/i386-expand.c
+++ b/gcc/config/i386/i386-expand.c
@@ -258,13 +258,13 @@ ix86_expand_move (machine_mode mode, rtx operands[])
 		op1 = machopic_legitimize_pic_address (op1, mode,
 						       temp == op1 ? 0 : temp);
 	    }
-	  if (op0 != op1 && GET_CODE (op0) != MEM)
+	  if (op0 != op1 && !MEM_P (op0))
 	    {
 	      rtx insn = gen_rtx_SET (op0, op1);
 	      emit_insn (insn);
 	      return;
 	    }
-	  if (GET_CODE (op0) == MEM)
+	  if (MEM_P (op0))
 	    op1 = force_reg (Pmode, op1);
 	  else
 	    {
diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c
index a5813a80bfa..86ef8bc0078 100644
--- a/gcc/config/ia64/ia64.c
+++ b/gcc/config/ia64/ia64.c
@@ -877,7 +877,7 @@ ia64_encode_section_info (tree decl, rtx rtl, int first)
 
   /* Careful not to prod global register variables.  */
   if (TREE_CODE (decl) == VAR_DECL
-      && GET_CODE (DECL_RTL (decl)) == MEM
+      && MEM_P (DECL_RTL (decl))
       && GET_CODE (XEXP (DECL_RTL (decl), 0)) == SYMBOL_REF
       && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
     ia64_encode_addr_area (decl, XEXP (rtl, 0));
@@ -892,9 +892,9 @@ ia64_move_ok (rtx dst, rtx src)
      memory_operand.  So check the code directly and don't worry about
      the validity of the underlying address, which should have been
      checked elsewhere anyway.  */
-  if (GET_CODE (dst) != MEM)
+  if (!MEM_P (dst))
     return 1;
-  if (GET_CODE (src) == MEM)
+  if (MEM_P (src))
     return 0;
   if (register_operand (src, VOIDmode))
     return 1;
@@ -917,7 +917,7 @@ ia64_load_pair_ok (rtx dst, rtx src)
   if (!REG_P (dst)
       || !(FP_REGNO_P (REGNO (dst)) && FP_REGNO_P (REGNO (dst) + 1)))
     return 0;
-  if (GET_CODE (src) != MEM || MEM_VOLATILE_P (src))
+  if (!MEM_P (src) || MEM_VOLATILE_P (src))
     return 0;
   switch (GET_CODE (XEXP (src, 0)))
     {
@@ -1586,7 +1586,7 @@ ia64_split_tmode_move (rtx operands[])
      load, or rws_access_regno will die.  And we must not generate a
      postmodify for the second load if the destination register 
      overlaps with the base register.  */
-  if (GET_CODE (operands[1]) == MEM
+  if (MEM_P (operands[1])
       && reg_overlap_mentioned_p (operands[0], operands[1]))
     {
       rtx base = XEXP (operands[1], 0);
@@ -1612,7 +1612,7 @@ ia64_split_tmode_move (rtx operands[])
   fixup[1] = ia64_split_tmode (out, operands[0], reversed, dead);
 
 #define MAYBE_ADD_REG_INC_NOTE(INSN, EXP)				\
-  if (GET_CODE (EXP) == MEM						\
+  if (MEM_P (EXP)						\
       && (GET_CODE (XEXP (EXP, 0)) == POST_MODIFY			\
 	  || GET_CODE (XEXP (EXP, 0)) == POST_INC			\
 	  || GET_CODE (XEXP (EXP, 0)) == POST_DEC))			\
@@ -1725,7 +1725,7 @@ ia64_expand_movxf_movrf (machine_mode mode, rtx operands[])
       if (register_operand (operands[1], mode))
 	operands[1] = spill_xfmode_rfmode_operand (operands[1], 1, mode);
 
-      gcc_assert (GET_CODE (operands[1]) == MEM);
+      gcc_assert (MEM_P (operands[1]));
 
       /* Don't word-swap when reading in the value.  */
       out[0] = gen_rtx_REG (DImode, REGNO (op0));
@@ -1757,7 +1757,7 @@ ia64_expand_movxf_movrf (machine_mode mode, rtx operands[])
 	{
 	  rtx in[2];
 
-	  gcc_assert (GET_CODE (operands[0]) == MEM);
+	  gcc_assert (MEM_P (operands[0]));
 
 	  /* Don't word-swap when writing out the value.  */
 	  in[0] = gen_rtx_REG (DImode, REGNO (operands[1]));
@@ -1778,7 +1778,7 @@ ia64_expand_movxf_movrf (machine_mode mode, rtx operands[])
 	  rtx memt, memx, in = operands[1];
 	  if (CONSTANT_P (in))
 	    in = validize_mem (force_const_mem (mode, in));
-	  if (GET_CODE (in) == MEM)
+	  if (MEM_P (in))
 	    memt = adjust_address (in, TImode, 0);
 	  else
 	    {
@@ -5923,7 +5923,7 @@ ia64_secondary_reload_class (enum reg_class rclass,
 
       /* This is needed if a pseudo used as a call_operand gets spilled to a
 	 stack slot.  */
-      if (GET_CODE (x) == MEM)
+      if (MEM_P (x))
 	return GR_REGS;
       break;
 
@@ -5940,7 +5940,7 @@ ia64_secondary_reload_class (enum reg_class rclass,
 	 register_operand when INSN_SCHEDULING is defined.  Or alternatively,
 	 stop the paradoxical subreg stupidity in the *_operand functions
 	 in recog.c.  */
-      if (GET_CODE (x) == MEM
+      if (MEM_P (x)
 	  && (GET_MODE (x) == SImode || GET_MODE (x) == HImode
 	      || GET_MODE (x) == QImode))
 	return GR_REGS;
@@ -5964,7 +5964,7 @@ ia64_secondary_reload_class (enum reg_class rclass,
 	 crtl->has_nonlocal_goto is true.  This is relatively
 	 common for C++ programs that use exceptions.  To reproduce,
 	 return NO_REGS and compile libstdc++.  */
-      if (GET_CODE (x) == MEM)
+      if (MEM_P (x))
 	return GR_REGS;
 
       /* This can happen when we take a BImode subreg of a DImode value,
@@ -9633,7 +9633,7 @@ ia64_st_address_bypass_p (rtx_insn *producer, rtx_insn *consumer)
   dest = ia64_single_set (consumer);
   gcc_assert (dest);
   mem = SET_DEST (dest);
-  gcc_assert (mem && GET_CODE (mem) == MEM);
+  gcc_assert (mem && MEM_P (mem));
   return reg_mentioned_p (reg, mem);
 }
 
@@ -9681,7 +9681,7 @@ ia64_ld_address_bypass_p (rtx_insn *producer, rtx_insn *consumer)
     }
 
   /* Note that LO_SUM is used for GOT loads.  */
-  gcc_assert (GET_CODE (mem) == LO_SUM || GET_CODE (mem) == MEM);
+  gcc_assert (GET_CODE (mem) == LO_SUM || MEM_P (mem));
 
   return reg_mentioned_p (reg, mem);
 }
diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md
index 5322e66e1be..d22817af05b 100644
--- a/gcc/config/ia64/ia64.md
+++ b/gcc/config/ia64/ia64.md
@@ -4587,7 +4587,7 @@
      element into a register without bothering to see whether that
      is necessary given the operand predicate.  Check for MEM just
      in case someone fixes this.  */
-  if (GET_CODE (op0) == MEM)
+  if (MEM_P (op0))
     addr = XEXP (op0, 0);
   else
     {
@@ -4604,7 +4604,7 @@
       set = single_set (last);
 
       gcc_assert (rtx_equal_p (SET_DEST (set), op0)
-		  && GET_CODE (SET_SRC (set)) == MEM);
+		  && MEM_P (SET_SRC (set)));
       addr = XEXP (SET_SRC (set), 0);
       gcc_assert (!rtx_equal_p (addr, op0));
     }
diff --git a/gcc/config/ia64/predicates.md b/gcc/config/ia64/predicates.md
index c1f3e09322c..4b78dcf4971 100644
--- a/gcc/config/ia64/predicates.md
+++ b/gcc/config/ia64/predicates.md
@@ -308,14 +308,14 @@
 ;; POST_MODIFY with a REG as displacement.
 (define_predicate "destination_operand"
   (and (match_operand 0 "nonimmediate_operand")
-       (match_test "GET_CODE (op) != MEM
+       (match_test "!MEM_P (op)
 		    || GET_CODE (XEXP (op, 0)) != POST_MODIFY
 		    || !REG_P (XEXP (XEXP (XEXP (op, 0), 1), 1))")))
 
 ;; Like destination_operand, but don't allow any post-increments.
 (define_predicate "not_postinc_destination_operand"
   (and (match_operand 0 "nonimmediate_operand")
-       (match_test "GET_CODE (op) != MEM
+       (match_test "!MEM_P (op)
         || GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != RTX_AUTOINC")))
 
 ;; Like memory_operand, but don't allow post-increments.
@@ -372,7 +372,7 @@
 ;; Like move_operand but don't allow post-increments.
 (define_predicate "not_postinc_move_operand"
   (and (match_operand 0 "move_operand")
-       (match_test "GET_CODE (op) != MEM
+       (match_test "!MEM_P (op)
         || GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != RTX_AUTOINC")))
 
 ;; True if OP is a register operand that is (or could be) a GR reg.
@@ -419,7 +419,7 @@
 {
   unsigned int regno;
 
-  if (GET_CODE (op) == MEM)
+  if (MEM_P (op))
     return true;
   if (SUBREG_P (op))
     op = SUBREG_REG (op);
@@ -434,7 +434,7 @@
 {
   unsigned int regno;
 
-  if (GET_CODE (op) == MEM)
+  if (MEM_P (op))
     return true;
   if (SUBREG_P (op))
     op = SUBREG_REG (op);
@@ -449,7 +449,7 @@
 {
   unsigned int regno;
 
-  if (GET_CODE (op) == MEM)
+  if (MEM_P (op))
     return true;
   if (SUBREG_P (op))
     op = SUBREG_REG (op);
diff --git a/gcc/config/iq2000/iq2000.c b/gcc/config/iq2000/iq2000.c
index 2092093b877..74e52a16c7b 100644
--- a/gcc/config/iq2000/iq2000.c
+++ b/gcc/config/iq2000/iq2000.c
@@ -469,7 +469,7 @@ iq2000_count_memory_refs (rtx op, int num)
     }
 
   /* Skip MEM if passed, otherwise handle movsi of address.  */
-  addr = (GET_CODE (op) != MEM) ? op : XEXP (op, 0);
+  addr = (!MEM_P (op)) ? op : XEXP (op, 0);
 
   /* Loop, going through the address RTL.  */
   do
diff --git a/gcc/config/iq2000/iq2000.md b/gcc/config/iq2000/iq2000.md
index 0ff9d01998a..ac34adf4c0f 100644
--- a/gcc/config/iq2000/iq2000.md
+++ b/gcc/config/iq2000/iq2000.md
@@ -510,10 +510,10 @@
   ""
   "
 {
-  if (optimize && GET_CODE (operands[1]) == MEM)
+  if (optimize && MEM_P (operands[1]))
     operands[1] = force_not_mem (operands[1]);
 
-  if (GET_CODE (operands[1]) != MEM)
+  if (!MEM_P (operands[1]))
     {
       rtx op1   = gen_lowpart (SImode, operands[1]);
       rtx temp  = gen_reg_rtx (SImode);
@@ -540,10 +540,10 @@
   ""
   "
 {
-  if (optimize && GET_CODE (operands[1]) == MEM)
+  if (optimize && MEM_P (operands[1]))
     operands[1] = force_not_mem (operands[1]);
 
-  if (GET_CODE (operands[1]) != MEM)
+  if (!MEM_P (operands[1]))
     {
       rtx op0   = gen_lowpart (SImode, operands[0]);
       rtx op1   = gen_lowpart (SImode, operands[1]);
@@ -572,10 +572,10 @@
   ""
   "
 {
-  if (optimize && GET_CODE (operands[1]) == MEM)
+  if (optimize && MEM_P (operands[1]))
     operands[1] = force_not_mem (operands[1]);
 
-  if (GET_CODE (operands[1]) != MEM)
+  if (!MEM_P (operands[1]))
     {
       rtx op1   = gen_lowpart (SImode, operands[1]);
       rtx temp  = gen_reg_rtx (SImode);
@@ -828,8 +828,8 @@
 {
   if (!reload_in_progress
       && !reload_completed
-      && GET_CODE (operands[0]) == MEM
-      && (GET_CODE (operands[1]) == MEM
+      && MEM_P (operands[0])
+      && (MEM_P (operands[1])
          || CONST_DOUBLE_P (operands[1])))
     operands[1] = copy_to_mode_reg (SFmode, operands[1]);
 
diff --git a/gcc/config/iq2000/predicates.md b/gcc/config/iq2000/predicates.md
index c8f4ef37fc8..e75fb05cac7 100644
--- a/gcc/config/iq2000/predicates.md
+++ b/gcc/config/iq2000/predicates.md
@@ -118,7 +118,7 @@
   rtx addr, plus0, plus1;
 
   /* Eliminate non-memory operations.  */
-  if (GET_CODE (op) != MEM)
+  if (!MEM_P (op))
     return 0;
 
   /* Dword operations really put out 2 instructions, so eliminate them.  */
diff --git a/gcc/config/lm32/lm32.md b/gcc/config/lm32/lm32.md
index e52354eb8d8..76fe95bbf18 100644
--- a/gcc/config/lm32/lm32.md
+++ b/gcc/config/lm32/lm32.md
@@ -105,7 +105,7 @@
 {
   if (can_create_pseudo_p ())
     {
-      if (GET_CODE (operand0) == MEM)
+      if (MEM_P (operand0))
         {
           /* Source operand for store must be in a register.  */
           operands[1] = force_reg (QImode, operands[1]);
@@ -121,7 +121,7 @@
 {
   if (can_create_pseudo_p ())
     {
-      if (GET_CODE (operands[0]) == MEM)
+      if (MEM_P (operands[0]))
         {
           /* Source operand for store must be in a register.  */
           operands[1] = force_reg (HImode, operands[1]);
@@ -137,9 +137,9 @@
 {
   if (can_create_pseudo_p ())
     {
-      if (GET_CODE (operands[0]) == MEM 
+      if (MEM_P (operands[0]) 
 	  || (SUBREG_P (operands[0]) 
-	      && GET_CODE (SUBREG_REG (operands[0])) == MEM))
+	      && MEM_P (SUBREG_REG (operands[0]))))
         {
           /* Source operand for store must be in a register.  */
           operands[1] = force_reg (SImode, operands[1]);
diff --git a/gcc/config/m32c/m32c.c b/gcc/config/m32c/m32c.c
index 922ea03ce80..4a122a76908 100644
--- a/gcc/config/m32c/m32c.c
+++ b/gcc/config/m32c/m32c.c
@@ -131,7 +131,7 @@ static GTY(()) rtx patternr[30];
 static int
 far_addr_space_p (rtx x)
 {
-  if (GET_CODE (x) != MEM)
+  if (!MEM_P (x))
     return 0;
 #if DEBUG0
   fprintf(stderr, "\033[35mfar_addr_space: "); debug_rtx(x);
@@ -694,7 +694,7 @@ m32c_preferred_reload_class (rtx x, reg_class_t rclass)
   fprintf (stderr, "%s\n", class_names[rclass]);
   debug_rtx (x);
 
-  if (GET_CODE (x) == MEM
+  if (MEM_P (x)
       && GET_CODE (XEXP (x, 0)) == PLUS
       && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
     fprintf (stderr, "Glorm!\n");
@@ -754,7 +754,7 @@ m32c_secondary_reload_class (int rclass, machine_mode mode, rtx x)
   debug_rtx (x);
 #endif
   if (mode == QImode
-      && GET_CODE (x) == MEM && (cc & ~class_contents[R23_REGS][0]) == 0)
+      && MEM_P (x) && (cc & ~class_contents[R23_REGS][0]) == 0)
     return QI_REGS;
   if (reg_classes_intersect_p (rclass, CR_REGS)
       && REG_P (x)
@@ -875,7 +875,7 @@ m32c_matches_constraint_p (rtx value, int constraint)
     {
       /* This is the common "src/dest" address */
       rtx r;
-      if (GET_CODE (value) == MEM && CONSTANT_P (XEXP (value, 0)))
+      if (MEM_P (value) && CONSTANT_P (XEXP (value, 0)))
 	return true;
       if (RTX_IS ("ms") || RTX_IS ("m+si"))
 	return true;
@@ -1680,7 +1680,7 @@ m32c_legitimate_address_p (machine_mode mode, rtx x, bool strict)
   /* This is the double indirection detection, but it currently
      doesn't work as cleanly as this code implies, so until we've had
      a chance to debug it, leave it disabled.  */
-  if (TARGET_A24 && GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) != PLUS)
+  if (TARGET_A24 && MEM_P (x) && GET_CODE (XEXP (x, 0)) != PLUS)
     {
 #if DEBUG_DOUBLE
       fprintf (stderr, "double indirect\n");
@@ -2809,7 +2809,7 @@ m32c_print_operand_punct_valid_p (unsigned char c)
 static void
 m32c_print_operand_address (FILE * stream, machine_mode /*mode*/, rtx address)
 {
-  if (GET_CODE (address) == MEM)
+  if (MEM_P (address))
     address = XEXP (address, 0);
   else
     /* cf: gcc.dg/asm-4.c.  */
@@ -3132,7 +3132,7 @@ m32c_illegal_subreg_p (rtx op)
   unsigned int i;
   machine_mode src_mode, dest_mode;
 
-  if (GET_CODE (op) == MEM
+  if (MEM_P (op)
       && ! m32c_legitimate_address_p (Pmode, XEXP (op, 0), false))
     {
       return true;
@@ -3204,8 +3204,8 @@ m32c_mov_ok (rtx * operands, machine_mode mode ATTRIBUTE_UNUSED)
   if (SUBREG_P (op1))
     op1 = XEXP (op1, 0);
 
-  if (GET_CODE (op0) == MEM
-      && GET_CODE (op1) == MEM
+  if (MEM_P (op0)
+      && MEM_P (op1)
       && ! reload_completed)
     {
 #if DEBUG_MOV_OK
@@ -3246,7 +3246,7 @@ m32c_subreg (machine_mode outer,
      just rewrite them.  */
   if (SUBREG_P (x)
       && SUBREG_BYTE (x) == 0
-      && GET_CODE (SUBREG_REG (x)) == MEM
+      && MEM_P (SUBREG_REG (x))
       && (GET_MODE_SIZE (GET_MODE (x))
 	  == GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
     {
@@ -3256,12 +3256,12 @@ m32c_subreg (machine_mode outer,
     }
 
   /* Push/pop get done as smaller push/pops.  */
-  if (GET_CODE (x) == MEM
+  if (MEM_P (x)
       && (GET_CODE (XEXP (x, 0)) == PRE_DEC
 	  || GET_CODE (XEXP (x, 0)) == POST_INC))
     return gen_rtx_MEM (outer, XEXP (x, 0));
   if (SUBREG_P (x)
-      && GET_CODE (XEXP (x, 0)) == MEM
+      && MEM_P (XEXP (x, 0))
       && (GET_CODE (XEXP (XEXP (x, 0), 0)) == PRE_DEC
 	  || GET_CODE (XEXP (XEXP (x, 0), 0)) == POST_INC))
     return gen_rtx_MEM (outer, XEXP (XEXP (x, 0), 0));
@@ -3270,7 +3270,7 @@ m32c_subreg (machine_mode outer,
     {
       rtx r = simplify_gen_subreg (outer, x, inner, byte);
       if (SUBREG_P (r)
-	  && GET_CODE (x) == MEM
+	  && MEM_P (x)
 	  && MEM_VOLATILE_P (x))
 	{
 	  /* Volatile MEMs don't get simplified, but we need them to
@@ -3334,7 +3334,7 @@ m32c_prepare_move (rtx * operands, machine_mode mode)
     }
   if (TARGET_A16 && mode == PSImode)
     return m32c_split_move (operands, mode, 1);
-  if ((GET_CODE (operands[0]) == MEM)
+  if ((MEM_P (operands[0]))
       && (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY))
     {
       rtx pmv = XEXP (operands[0], 0);
@@ -3369,7 +3369,7 @@ m32c_split_psi_p (rtx * operands)
 #endif
       return 1;
     }
-  if (GET_CODE (operands[1]) == MEM
+  if (MEM_P (operands[1])
       && GET_CODE (XEXP (operands[1], 0)) == POST_INC)
     {
 #if DEBUG_SPLIT
@@ -3446,7 +3446,7 @@ m32c_split_move (rtx * operands, machine_mode mode, int split_all)
   if (TARGET_A24
       && split_all != 3
       && (mode == SImode || mode == PSImode)
-      && !(GET_CODE (operands[1]) == MEM
+      && !(MEM_P (operands[1])
 	   && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
     return 0;
 
@@ -3462,7 +3462,7 @@ m32c_split_move (rtx * operands, machine_mode mode, int split_all)
     }
 
   /* Split pushes by emitting a sequence of smaller pushes.  */
-  if (GET_CODE (d[0]) == MEM && GET_CODE (XEXP (d[0], 0)) == PRE_DEC)
+  if (MEM_P (d[0]) && GET_CODE (XEXP (d[0], 0)) == PRE_DEC)
     {
       for (si = parts - 1; si >= 0; si--)
 	{
@@ -3476,7 +3476,7 @@ m32c_split_move (rtx * operands, machine_mode mode, int split_all)
       rv = 1;
     }
   /* Likewise for pops.  */
-  else if (GET_CODE (s[0]) == MEM && GET_CODE (XEXP (s[0], 0)) == POST_INC)
+  else if (MEM_P (s[0]) && GET_CODE (XEXP (s[0], 0)) == POST_INC)
     {
       for (di = 0; di < parts; di++)
 	{
@@ -3915,7 +3915,7 @@ m32c_expand_insv (rtx *operands)
     }
 
   if (!can_create_pseudo_p ()
-      || (GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0)))
+      || (MEM_P (op0) && MEM_VOLATILE_P (op0)))
     src0 = op0;
   else
     {
@@ -3925,7 +3925,7 @@ m32c_expand_insv (rtx *operands)
 
   if (GET_MODE (op0) == HImode
       && INTVAL (operands[2]) >= 8
-      && GET_CODE (op0) == MEM)
+      && MEM_P (op0))
     {
       /* We are little endian.  */
       rtx new_mem = gen_rtx_MEM (QImode, plus_constant (Pmode,
@@ -4364,8 +4364,8 @@ m32c_compare_redundant (rtx_insn *cmp, rtx *operands)
 
     /* Check for comparisons against memory - between volatiles and
        aliases, we just can't risk this one.  */
-    if (GET_CODE (operands[0]) == MEM
-	|| GET_CODE (operands[0]) == MEM)
+    if (MEM_P (operands[0])
+	|| MEM_P (operands[0]))
       {
 #if DEBUG_CMP
 	fprintf(stderr, "comparisons with memory:\n");
diff --git a/gcc/config/m32c/predicates.md b/gcc/config/m32c/predicates.md
index 2c66da5f284..48e9ee1f5af 100644
--- a/gcc/config/m32c/predicates.md
+++ b/gcc/config/m32c/predicates.md
@@ -151,7 +151,7 @@
 (define_predicate "mra_nopp_operand"
   (match_operand 0 "mra_operand" "")
 {
-  if (GET_CODE (op) == MEM
+  if (MEM_P (op)
       && (GET_CODE (XEXP (op, 0)) == PRE_DEC
 	  || (GET_CODE (XEXP (op, 0)) == POST_INC)))
     return 0;
diff --git a/gcc/config/m68k/m68k.c b/gcc/config/m68k/m68k.c
index 0fb4b059daa..0f4c1f4fda9 100644
--- a/gcc/config/m68k/m68k.c
+++ b/gcc/config/m68k/m68k.c
@@ -3082,10 +3082,10 @@ output_move_himode (rtx *operands)
     {
       if (operands[1] == const0_rtx
 	  && (DATA_REG_P (operands[0])
-	      || GET_CODE (operands[0]) == MEM)
+	      || MEM_P (operands[0]))
 	  /* clr insns on 68000 read before writing.  */
 	  && ((TARGET_68010 || TARGET_COLDFIRE)
-	      || !(GET_CODE (operands[0]) == MEM
+	      || !(MEM_P (operands[0])
 		   && MEM_VOLATILE_P (operands[0]))))
 	return "clr%.w %0";
       else if (operands[1] == const0_rtx
@@ -3111,7 +3111,7 @@ output_move_qimode (rtx *operands)
      byte pushes.  The 5200 (ColdFire) does not do this.  */
   
   /* This case is generated by pushqi1 pattern now.  */
-  gcc_assert (!(GET_CODE (operands[0]) == MEM
+  gcc_assert (!(MEM_P (operands[0])
 		&& GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
 		&& XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx
 		&& ! ADDRESS_REG_P (operands[1])
@@ -3120,7 +3120,7 @@ output_move_qimode (rtx *operands)
   /* clr and st insns on 68000 read before writing.  */
   if (!ADDRESS_REG_P (operands[0])
       && ((TARGET_68010 || TARGET_COLDFIRE)
-	  || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
+	  || !(MEM_P (operands[0]) && MEM_VOLATILE_P (operands[0]))))
     {
       if (operands[1] == const0_rtx)
 	return "clr%.b %0";
@@ -3154,7 +3154,7 @@ output_move_stricthi (rtx *operands)
   if (operands[1] == const0_rtx
       /* clr insns on 68000 read before writing.  */
       && ((TARGET_68010 || TARGET_COLDFIRE)
-	  || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
+	  || !(MEM_P (operands[0]) && MEM_VOLATILE_P (operands[0]))))
     return "clr%.w %0";
   return "move%.w %1,%0";
 }
@@ -3165,7 +3165,7 @@ output_move_strictqi (rtx *operands)
   if (operands[1] == const0_rtx
       /* clr insns on 68000 read before writing.  */
       && ((TARGET_68010 || TARGET_COLDFIRE)
-          || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
+          || !(MEM_P (operands[0]) && MEM_VOLATILE_P (operands[0]))))
     return "clr%.b %0";
   return "move%.b %1,%0";
 }
@@ -3219,7 +3219,7 @@ handle_move_double (rtx operands[2],
     optype0 = POPOP;
   else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
     optype0 = PUSHOP;
-  else if (GET_CODE (operands[0]) == MEM)
+  else if (MEM_P (operands[0]))
     optype0 = MEMOP;
   else
     optype0 = RNDOP;
@@ -3234,7 +3234,7 @@ handle_move_double (rtx operands[2],
     optype1 = POPOP;
   else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
     optype1 = PUSHOP;
-  else if (GET_CODE (operands[1]) == MEM)
+  else if (MEM_P (operands[1]))
     optype1 = MEMOP;
   else
     optype1 = RNDOP;
@@ -3714,11 +3714,11 @@ emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
       operand1 = alter_subreg (&temp, true);
     }
 
-  if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
+  if (scratch_reg && reload_in_progress && MEM_P (operand0)
       && ((tem = find_replacement (&XEXP (operand0, 0)))
 	  != XEXP (operand0, 0)))
     operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
-  if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
+  if (scratch_reg && reload_in_progress && MEM_P (operand1)
       && ((tem = find_replacement (&XEXP (operand1, 0)))
 	  != XEXP (operand1, 0)))
     operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
@@ -3726,10 +3726,10 @@ emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
   /* Handle secondary reloads for loads/stores of FP registers where
      the address is symbolic by using the scratch register */
   if (fp_reg_operand (operand0, mode)
-      && ((GET_CODE (operand1) == MEM
+      && ((MEM_P (operand1)
 	   && ! memory_address_p (DFmode, XEXP (operand1, 0)))
 	  || ((SUBREG_P (operand1)
-	       && GET_CODE (XEXP (operand1, 0)) == MEM
+	       && MEM_P (XEXP (operand1, 0))
 	       && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
       && scratch_reg)
     {
@@ -3757,10 +3757,10 @@ emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
       return 1;
     }
   else if (fp_reg_operand (operand1, mode)
-	   && ((GET_CODE (operand0) == MEM
+	   && ((MEM_P (operand0)
 		&& ! memory_address_p (DFmode, XEXP (operand0, 0)))
 	       || ((SUBREG_P (operand0))
-		   && GET_CODE (XEXP (operand0, 0)) == MEM
+		   && MEM_P (XEXP (operand0, 0))
 		   && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
 	   && scratch_reg)
     {
@@ -3839,7 +3839,7 @@ split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
 
       /* simplify_subreg refuses to split volatile memory addresses,
 	 but we still have to handle it.  */
-      if (GET_CODE (op) == MEM)
+      if (MEM_P (op))
 	{
 	  lo_half[num] = adjust_address (op, SImode, 4);
 	  hi_half[num] = adjust_address (op, SImode, 0);
@@ -4184,7 +4184,7 @@ notice_update_cc (rtx exp, rtx insn)
 	       && !FP_REG_P (SET_SRC (exp))
 	       && GET_MODE_SIZE (GET_MODE (SET_SRC (exp))) > 4
 	       && (REG_P (SET_SRC (exp))
-		   || GET_CODE (SET_SRC (exp)) == MEM
+		   || MEM_P (SET_SRC (exp))
 		   || CONST_DOUBLE_P (SET_SRC (exp))))
 	CC_STATUS_INIT; 
       else if (SET_DEST (exp) != pc_rtx)
@@ -4245,7 +4245,7 @@ notice_update_cc (rtx exp, rtx insn)
       && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))
     cc_status.value2 = 0;
   /* Check for PRE_DEC in dest modifying a register used in src.  */
-  if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM
+  if (cc_status.value1 && MEM_P (cc_status.value1)
       && GET_CODE (XEXP (cc_status.value1, 0)) == PRE_DEC
       && cc_status.value2
       && reg_overlap_mentioned_p (XEXP (XEXP (cc_status.value1, 0), 0),
@@ -4498,7 +4498,7 @@ print_operand (FILE *file, rtx op, int letter)
       else
 	fputs (M68K_REGNAME(REGNO (op)), file);
     }
-  else if (GET_CODE (op) == MEM)
+  else if (MEM_P (op))
     {
       output_address (GET_MODE (op), XEXP (op, 0));
       if (letter == 'd' && ! TARGET_68020
diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index ce4f39c953b..c995f4469c3 100644
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -504,10 +504,10 @@
                  (match_operand:SI 1 "general_operand" "mr,ma,KTr,Ksr,>")))]
   "!TARGET_COLDFIRE"
 {
-  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
+  if (MEM_P (operands[0]) && MEM_P (operands[1]))
     return "cmpm%.l %1,%0";
   if (REG_P (operands[1])
-      || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
+      || (!REG_P (operands[0]) && !MEM_P (operands[0])))
     {
       cc_status.flags |= CC_REVERSED; /*|*/
       return "cmp%.l %d0,%d1";
@@ -527,7 +527,7 @@
   "TARGET_COLDFIRE"
 {
   if (REG_P (operands[1])
-      || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
+      || (!REG_P (operands[0]) && !MEM_P (operands[0])))
     {
       cc_status.flags |= CC_REVERSED; /*|*/
       return "cmp%.l %d0,%d1";
@@ -564,10 +564,10 @@
                  (match_operand:HI 1 "general_operand" "d,rnm,m,n,>")))]
   "!TARGET_COLDFIRE"
 {
-  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
+  if (MEM_P (operands[0]) && MEM_P (operands[1]))
     return "cmpm%.w %1,%0";
   if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
-      || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
+      || (!REG_P (operands[0]) && !MEM_P (operands[0])))
     {
       cc_status.flags |= CC_REVERSED; /*|*/
       return "cmp%.w %d0,%d1";
@@ -603,10 +603,10 @@
                  (match_operand:QI 1 "general_operand" "dm,nd,>")))]
   "!TARGET_COLDFIRE"
 {
-  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
+  if (MEM_P (operands[0]) && MEM_P (operands[1]))
     return "cmpm%.b %1,%0";
   if (REG_P (operands[1])
-      || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
+      || (!REG_P (operands[0]) && !MEM_P (operands[0])))
     {
       cc_status.flags |= CC_REVERSED; /*|*/
       return "cmp%.b %d0,%d1";
@@ -770,7 +770,7 @@
   "!TARGET_COLDFIRE
    && !(REG_P (operands[0]) && !IN_RANGE (INTVAL (operands[1]), 0, 31))"
 {
-  if (GET_CODE (operands[0]) == MEM)
+  if (MEM_P (operands[0]))
     {
       operands[0] = adjust_address (operands[0], QImode,
 				    INTVAL (operands[1]) / 8);
@@ -794,7 +794,7 @@
   "TARGET_COLDFIRE
    && !(REG_P (operands[0]) && !IN_RANGE (INTVAL (operands[1]), 0, 31))"
 {
-  if (GET_CODE (operands[0]) == MEM)
+  if (MEM_P (operands[0]))
     {
       operands[0] = adjust_address (operands[0], QImode,
 				    INTVAL (operands[1]) / 8);
@@ -936,7 +936,7 @@
 	 the m68k doesn't consider PC-relative addresses to be writable.  */
       if (symbolic_operand (operands[0], SImode))
 	operands[0] = force_reg (SImode, XEXP (operands[0], 0));
-      else if (GET_CODE (operands[0]) == MEM
+      else if (MEM_P (operands[0])
 	       && symbolic_operand (XEXP (operands[0], 0), SImode))
 	operands[0] = gen_rtx_MEM (SImode,
 			       force_reg (SImode, XEXP (operands[0], 0)));
@@ -1184,7 +1184,7 @@
   if (operands[1] == CONST0_RTX (SFmode)
       /* clr insns on 68000 read before writing.  */
       && ((TARGET_68010 || TARGET_COLDFIRE)
-	  || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
+	  || !(MEM_P (operands[0]) && MEM_VOLATILE_P (operands[0]))))
     {
       if (ADDRESS_REG_P (operands[0]))
 	{
@@ -1231,7 +1231,7 @@
         else
           output_asm_insn ("clr%.l %0", xoperands);
       } else
-        if (GET_CODE (operands[0]) == MEM
+        if (MEM_P (operands[0])
             && symbolic_operand (XEXP (operands[0], 0), SImode))
           output_asm_insn ("move%.l %1,%-;move%.l %+,%0", xoperands);
         else
@@ -1416,7 +1416,7 @@
 	{
 	  /* Don't allow writes to memory except via a register; the
 	     m68k doesn't consider PC-relative addresses to be writable.  */
-	  if (GET_CODE (operands[0]) == MEM
+	  if (MEM_P (operands[0])
 	      && symbolic_operand (XEXP (operands[0], 0), SImode))
 	    operands[0] = gen_rtx_MEM (XFmode,
 				   force_reg (SImode, XEXP (operands[0], 0)));
@@ -1588,7 +1588,7 @@
       CC_STATUS_INIT;
       return "move%.l %1,%0";
     }
-  if (GET_CODE (operands[1]) == MEM)
+  if (MEM_P (operands[1]))
     operands[1] = adjust_address (operands[1], QImode, 3);
   return "move%.b %1,%0";
 })
@@ -1600,7 +1600,7 @@
   "!TARGET_COLDFIRE"
 {
   if (REG_P (operands[0])
-      && (GET_CODE (operands[1]) == MEM
+      && (MEM_P (operands[1])
 	  || CONST_INT_P (operands[1])))
     {
       /* Must clear condition codes, since the move.w bases them on
@@ -1615,7 +1615,7 @@
       CC_STATUS_INIT;
       return "move%.l %1,%0";
     }
-  if (GET_CODE (operands[1]) == MEM)
+  if (MEM_P (operands[1]))
     operands[1] = adjust_address (operands[1], QImode, 1);
   return "move%.b %1,%0";
 })
@@ -1633,7 +1633,7 @@
       CC_STATUS_INIT;
       return "move%.l %1,%0";
     }
-  if (GET_CODE (operands[1]) == MEM)
+  if (MEM_P (operands[1]))
     operands[1] = adjust_address (operands[1], QImode, 2);
   return "move%.w %1,%0";
 })
@@ -1709,15 +1709,15 @@
 	(zero_extend:DI (match_operand:SI 1 "nonimmediate_src_operand" "")))]
   ""
 {
-  if (GET_CODE (operands[0]) == MEM
-      && GET_CODE (operands[1]) == MEM)
+  if (MEM_P (operands[0])
+      && MEM_P (operands[1]))
     operands[1] = force_reg (SImode, operands[1]);
 })
 
 (define_insn_and_split "*zero_extendsidi2"
   [(set (match_operand:DI 0 "nonimmediate_operand" "")
 	(zero_extend:DI (match_operand:SI 1 "nonimmediate_src_operand" "")))]
-  "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
+  "!MEM_P (operands[0]) || !MEM_P (operands[1])"
   "#"
   ""
   [(set (match_dup 2)
@@ -2278,7 +2278,7 @@
     operands[4] = operands[1];
   else
     operands[4] = adjust_address (operands[1], SImode, 4);
-  if (GET_CODE (operands[1]) == MEM
+  if (MEM_P (operands[1])
    && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
     output_asm_insn ("move%.l %4,%3", operands);
   output_asm_insn ("move%.l %1,%0\;smi %2", operands);
@@ -2286,7 +2286,7 @@
     output_asm_insn ("extb%.l %2", operands);
   else
     output_asm_insn ("ext%.w %2\;ext%.l %2", operands);
-  if (GET_CODE (operands[1]) != MEM
+  if (!MEM_P (operands[1])
    || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)
     output_asm_insn ("move%.l %4,%3", operands);
   return "sub%.l %2,%3\;subx%.l %2,%0";
@@ -2366,7 +2366,7 @@
     {
       if (DATA_REG_P (operands[2]))
 	return "add%.l %R2,%R0\;addx%.l %2,%0";
-      else if (GET_CODE (operands[2]) == MEM
+      else if (MEM_P (operands[2])
 	  && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
 	return "move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0";
       else
@@ -2411,7 +2411,7 @@
     }
   else
     {
-      gcc_assert (GET_CODE (operands[0]) == MEM);
+      gcc_assert (MEM_P (operands[0]));
       CC_STATUS_INIT;
       if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
 	{
@@ -2442,7 +2442,7 @@
 {
   operands[2] = operands[0];
   operands[3] = gen_label_rtx();
-  if (GET_CODE (operands[0]) == MEM)
+  if (MEM_P (operands[0]))
     {
       if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
         operands[0] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
@@ -2863,7 +2863,7 @@
     {
       if (DATA_REG_P (operands[2]))
 	return "sub%.l %R2,%R0\;subx%.l %2,%0";
-      else if (GET_CODE (operands[2]) == MEM
+      else if (MEM_P (operands[2])
 	  && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
 	{
 	  return "move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0";
@@ -2910,7 +2910,7 @@
     }
   else
     {
-      gcc_assert (GET_CODE (operands[0]) == MEM);
+      gcc_assert (MEM_P (operands[0]));
       CC_STATUS_INIT;
       if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
 	{
@@ -3724,7 +3724,7 @@
   if (GET_MODE (operands[1]) == SImode)
     return "or%.l %1,%0";
   byte_mode = (GET_MODE (operands[1]) == QImode);
-  if (GET_CODE (operands[0]) == MEM)
+  if (MEM_P (operands[0]))
     operands[0] = adjust_address (operands[0], byte_mode ? QImode : HImode,
 				  byte_mode ? 3 : 2);
   if (byte_mode)
@@ -3829,7 +3829,7 @@
 
   CC_STATUS_INIT;
   byte_mode = (GET_MODE (operands[1]) == QImode);
-  if (GET_CODE (operands[0]) == MEM)
+  if (MEM_P (operands[0]))
     operands[0] = adjust_address (operands[0], byte_mode ? QImode : HImode,
 				  byte_mode ? 3 : 2);
   if (byte_mode)
@@ -4380,7 +4380,7 @@
   ""
 {
   CC_STATUS_INIT;
-  if (GET_CODE (operands[0]) == MEM)
+  if (MEM_P (operands[0]))
     {
     if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
       return "clr%.l %0\;move%.w %1,%2\;move%.l %2,%0";
@@ -6782,7 +6782,7 @@
   CC_STATUS_INIT;
   if (DATA_REG_P (operands[0]))
     return "dbra %0,%l1";
-  if (GET_CODE (operands[0]) == MEM)
+  if (MEM_P (operands[0]))
     return "subq%.w #1,%0\;jcc %l1";
   return "subq%.w #1,%0\;cmp%.w #-1,%0\;jne %l1";
 })
@@ -6802,7 +6802,7 @@
   CC_STATUS_INIT;
   if (DATA_REG_P (operands[0]))
     return "dbra %0,%l1\;clr%.w %0\;subq%.l #1,%0\;jcc %l1";
-  if (GET_CODE (operands[0]) == MEM)
+  if (MEM_P (operands[0]))
     return "subq%.l #1,%0\;jcc %l1";
   return "subq%.l #1,%0\;cmp%.l #-1,%0\;jne %l1";
 })
@@ -6825,7 +6825,7 @@
   CC_STATUS_INIT;
   if (DATA_REG_P (operands[0]))
     return "dbra %0,%l1";
-  if (GET_CODE (operands[0]) == MEM)
+  if (MEM_P (operands[0]))
     return "subq%.w #1,%0\;jcc %l1";
   return "subq%.w #1,%0\;cmp%.w #-1,%0\;jne %l1";
 })
@@ -6860,7 +6860,7 @@
   CC_STATUS_INIT;
   if (DATA_REG_P (operands[0]))
     return "dbra %0,%l1\;clr%.w %0\;subq%.l #1,%0\;jcc %l1";
-  if (GET_CODE (operands[0]) == MEM)
+  if (MEM_P (operands[0]))
     return "subq%.l #1,%0\;jcc %l1";
   return "subq%.l #1,%0\;cmp%.l #-1,%0\;jne %l1";
 })
diff --git a/gcc/config/m68k/predicates.md b/gcc/config/m68k/predicates.md
index a90bf61a948..3238211a0de 100644
--- a/gcc/config/m68k/predicates.md
+++ b/gcc/config/m68k/predicates.md
@@ -25,7 +25,7 @@
   (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem")
 {
   if (TARGET_PCREL
-      && GET_CODE (op) == MEM
+      && MEM_P (op)
       && (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
 	  || GET_CODE (XEXP (op, 0)) == LABEL_REF
 	  || GET_CODE (XEXP (op, 0)) == CONST))
@@ -40,7 +40,7 @@
 (define_predicate "nonimmediate_src_operand"
   (match_code "subreg,reg,mem")
 {
-  if (TARGET_PCREL && GET_CODE (op) == MEM
+  if (TARGET_PCREL && MEM_P (op)
       && (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
 	  || GET_CODE (XEXP (op, 0)) == LABEL_REF
 	  || GET_CODE (XEXP (op, 0)) == CONST))
@@ -54,7 +54,7 @@
 (define_predicate "memory_src_operand"
   (match_code "subreg,mem")
 {
-  if (TARGET_PCREL && GET_CODE (op) == MEM
+  if (TARGET_PCREL && MEM_P (op)
       && (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
 	  || GET_CODE (XEXP (op, 0)) == LABEL_REF
 	  || GET_CODE (XEXP (op, 0)) == CONST))
diff --git a/gcc/config/mcore/mcore.c b/gcc/config/mcore/mcore.c
index 4df4551fd95..30d8c8b7c58 100644
--- a/gcc/config/mcore/mcore.c
+++ b/gcc/config/mcore/mcore.c
@@ -1291,7 +1291,7 @@ mcore_output_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
 	  else 
             return "mov\t%0,%1";                /* r-r*/
 	}
-      else if (GET_CODE (src) == MEM)
+      else if (MEM_P (src))
 	{
 	  if (GET_CODE (XEXP (src, 0)) == LABEL_REF) 
             return "lrw\t%0,[%1]";              /* a-R */
@@ -1326,7 +1326,7 @@ mcore_output_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
       else
 	return "lrw\t%0, %1";                /* Into the literal pool.  */
     }
-  else if (GET_CODE (dst) == MEM)               /* m-r */
+  else if (MEM_P (dst))               /* m-r */
     switch (GET_MODE (dst))
       {
       case E_SImode:
@@ -1365,7 +1365,7 @@ mcore_output_movedouble (rtx operands[], machine_mode mode ATTRIBUTE_UNUSED)
 	  else
 	    return "mov	%0,%1\n\tmov	%R0,%R1";
 	}
-      else if (GET_CODE (src) == MEM)
+      else if (MEM_P (src))
 	{
 	  rtx memexp = XEXP (src, 0);
 	  int dstreg = REGNO (dst);
@@ -1437,7 +1437,7 @@ mcore_output_movedouble (rtx operands[], machine_mode mode ATTRIBUTE_UNUSED)
       else
 	gcc_unreachable ();
     }
-  else if (GET_CODE (dst) == MEM && REG_P (src))
+  else if (MEM_P (dst) && REG_P (src))
     return "stw\t%1,%0\n\tstw\t%R1,%R0";
   else
     gcc_unreachable ();
@@ -1987,7 +1987,7 @@ mcore_expand_prolog (void)
 
       x = DECL_RTL (current_function_decl);
       
-      gcc_assert (GET_CODE (x) == MEM);
+      gcc_assert (MEM_P (x));
       
       x = XEXP (x, 0);
       
@@ -2911,7 +2911,7 @@ mcore_mark_dllexport (tree decl)
 
   rtlname = XEXP (DECL_RTL (decl), 0);
   
-  if (GET_CODE (rtlname) == MEM)
+  if (MEM_P (rtlname))
     rtlname = XEXP (rtlname, 0);
   gcc_assert (GET_CODE (rtlname) == SYMBOL_REF);
   oldname = XSTR (rtlname, 0);
@@ -2946,7 +2946,7 @@ mcore_mark_dllimport (tree decl)
 
   rtlname = XEXP (DECL_RTL (decl), 0);
   
-  if (GET_CODE (rtlname) == MEM)
+  if (MEM_P (rtlname))
     rtlname = XEXP (rtlname, 0);
   gcc_assert (GET_CODE (rtlname) == SYMBOL_REF);
   oldname = XSTR (rtlname, 0);
@@ -3032,8 +3032,8 @@ mcore_encode_section_info (tree decl, rtx rtl ATTRIBUTE_UNUSED, int first ATTRIB
   else if ((TREE_CODE (decl) == FUNCTION_DECL
 	    || TREE_CODE (decl) == VAR_DECL)
 	   && DECL_RTL (decl) != NULL_RTX
-	   && GET_CODE (DECL_RTL (decl)) == MEM
-	   && GET_CODE (XEXP (DECL_RTL (decl), 0)) == MEM
+	   && MEM_P (DECL_RTL (decl))
+	   && MEM_P (XEXP (DECL_RTL (decl), 0))
 	   && GET_CODE (XEXP (XEXP (DECL_RTL (decl), 0), 0)) == SYMBOL_REF
 	   && mcore_dllimport_name_p (XSTR (XEXP (XEXP (DECL_RTL (decl), 0), 0), 0)))
     {
diff --git a/gcc/config/mcore/mcore.md b/gcc/config/mcore/mcore.md
index c71cb67fdb6..dab98beca28 100644
--- a/gcc/config/mcore/mcore.md
+++ b/gcc/config/mcore/mcore.md
@@ -1185,7 +1185,7 @@
   ""
   "
 {
-  if (GET_CODE (operands[0]) == MEM)
+  if (MEM_P (operands[0]))
     operands[1] = force_reg (SImode, operands[1]);
 }")
 
@@ -1207,7 +1207,7 @@
   ""
   "
 {
-  if (GET_CODE (operands[0]) == MEM)
+  if (MEM_P (operands[0]))
     operands[1] = force_reg (HImode, operands[1]);
   else if (CONSTANT_P (operands[1])
 	   && (!CONST_INT_P (operands[1])
@@ -1240,7 +1240,7 @@
   ""
   "
 {
-  if (GET_CODE (operands[0]) == MEM)
+  if (MEM_P (operands[0]))
     operands[1] = force_reg (QImode, operands[1]);
   else if (CONSTANT_P (operands[1])
 	   && (!CONST_INT_P (operands[1])
@@ -1272,7 +1272,7 @@
   ""
   "
 {
-  if (GET_CODE (operands[0]) == MEM)
+  if (MEM_P (operands[0]))
     operands[1] = force_reg (DImode, operands[1]);
   else if (CONST_INT_P (operands[1])
            && ! CONST_OK_FOR_I (INTVAL (operands[1]))
@@ -1302,7 +1302,7 @@
   ""
   "
 {
-  if (GET_CODE (operands[0]) == MEM)
+  if (MEM_P (operands[0]))
     operands[1] = force_reg (SFmode, operands[1]);
 }")
 
@@ -1324,7 +1324,7 @@
   ""
   "
 {
-  if (GET_CODE (operands[0]) == MEM)
+  if (MEM_P (operands[0]))
     operands[1] = force_reg (DFmode, operands[1]);
 }")
 
@@ -1365,7 +1365,7 @@
      only if at least two registers.  The last register must be r15.  */
   if (!CONST_INT_P (operands[2])
       || INTVAL (operands[2]) < 2
-      || GET_CODE (operands[1]) != MEM
+      || !MEM_P (operands[1])
       || XEXP (operands[1], 0) != stack_pointer_rtx
       || !REG_P (operands[0])
       || REGNO (operands[0]) + INTVAL (operands[2]) != 16)
@@ -1403,7 +1403,7 @@
      only if at least two registers.  The last register must be r15.  */
   if (!CONST_INT_P (operands[2])
       || INTVAL (operands[2]) < 2
-      || GET_CODE (operands[0]) != MEM
+      || !MEM_P (operands[0])
       || XEXP (operands[0], 0) != stack_pointer_rtx
       || !REG_P (operands[1])
       || REGNO (operands[1]) + INTVAL (operands[2]) != 16)
@@ -1529,7 +1529,7 @@
   ""
   "
 {
-  if (GET_CODE (operands[0]) == MEM
+  if (MEM_P (operands[0])
       && ! register_operand (XEXP (operands[0], 0), SImode)
       && ! mcore_symbolic_address_p (XEXP (operands[0], 0)))
     operands[0] = gen_rtx_MEM (GET_MODE (operands[0]),
@@ -1551,7 +1551,7 @@
   ""
   "
 {
-  if (GET_CODE (operands[0]) == MEM
+  if (MEM_P (operands[0])
       && ! register_operand (XEXP (operands[0], 0), SImode)
       && ! mcore_symbolic_address_p (XEXP (operands[0], 0)))
     operands[1] = gen_rtx_MEM (GET_MODE (operands[1]),
diff --git a/gcc/config/mcore/predicates.md b/gcc/config/mcore/predicates.md
index 5bc901e55ea..d34f9f7125b 100644
--- a/gcc/config/mcore/predicates.md
+++ b/gcc/config/mcore/predicates.md
@@ -40,7 +40,7 @@
   (match_code "mem,const_int,reg,subreg,symbol_ref,label_ref,const")
 {
   /* Any (MEM LABEL_REF) is OK.  That is a pc-relative load.  */
-  if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == LABEL_REF)
+  if (MEM_P (op) && GET_CODE (XEXP (op, 0)) == LABEL_REF)
     return 1;
 
   return general_operand (op, mode);
@@ -69,7 +69,7 @@
   if (! reload_in_progress)
     return 0;
 
-  return GET_CODE (op) == MEM;
+  return MEM_P (op);
 })
 
 ;; Nonzero if OP is a valid source operand for an arithmetic insn.
@@ -263,7 +263,7 @@
   if (count <= 1
       || GET_CODE (XVECEXP (op, 0, 0)) != SET
       || !REG_P (SET_DEST (XVECEXP (op, 0, 0)))
-      || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
+      || !MEM_P (SET_SRC (XVECEXP (op, 0, 0))))
     return 0;
 
   dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
@@ -302,7 +302,7 @@
   /* Perform a quick check so we don't blow up below.  */
   if (count <= 1
       || GET_CODE (XVECEXP (op, 0, 0)) != SET
-      || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
+      || !MEM_P (SET_DEST (XVECEXP (op, 0, 0)))
       || !REG_P (SET_SRC (XVECEXP (op, 0, 0))))
     return 0;
 
@@ -317,7 +317,7 @@
 	  || !REG_P (SET_SRC (elt))
 	  || GET_MODE (SET_SRC (elt)) != SImode
 	  || REGNO (SET_SRC (elt)) != (unsigned) (src_regno + i)
-	  || GET_CODE (SET_DEST (elt)) != MEM
+	  || !MEM_P (SET_DEST (elt))
 	  || GET_MODE (SET_DEST (elt)) != SImode
 	  || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
 	  || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
index 800baefc070..e89c527cc41 100644
--- a/gcc/config/microblaze/microblaze.c
+++ b/gcc/config/microblaze/microblaze.c
@@ -288,7 +288,7 @@ simple_memory_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
   rtx addr, plus0, plus1;
 
   /* Eliminate non-memory operations.  */
-  if (GET_CODE (op) != MEM)
+  if (!MEM_P (op))
     return 0;
 
   /* dword operations really put out 2 instructions, so eliminate them.  */
@@ -348,7 +348,7 @@ double_memory_operand (rtx op, machine_mode mode)
 {
   rtx addr;
 
-  if (GET_CODE (op) != MEM || !memory_operand (op, mode))
+  if (!MEM_P (op) || !memory_operand (op, mode))
     {
       /* During reload, we accept a pseudo register if it has an
          appropriate memory address.  If we don't do this, we will
diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
index a4ffb50797f..a83d7ff2d80 100644
--- a/gcc/config/microblaze/microblaze.md
+++ b/gcc/config/microblaze/microblaze.md
@@ -1218,7 +1218,7 @@
   ""
   {
     if (flag_pic == 2) {
-      if (GET_CODE (operands[1]) == MEM 
+      if (MEM_P (operands[1]) 
           && !microblaze_legitimate_address_p (DFmode, XEXP (operands[1],0), 0))
       {
         rtx ptr_reg;
diff --git a/gcc/config/mmix/mmix.md b/gcc/config/mmix/mmix.md
index bf28b63a16b..70ac4997705 100644
--- a/gcc/config/mmix/mmix.md
+++ b/gcc/config/mmix/mmix.md
@@ -521,7 +521,7 @@ DIVU %1,%1,%2\;GET %0,:rR\;NEGU %2,0,%0\;CSNN %0,$255,%2")
   ""
   "
 {
-  if (GET_CODE (operands[0]) != MEM)
+  if (!MEM_P (operands[0]))
     {
       rtx stack_slot;
 
@@ -555,7 +555,7 @@ DIVU %1,%1,%2\;GET %0,:rR\;NEGU %2,0,%0\;CSNN %0,$255,%2")
   ""
   "
 {
-  if (GET_CODE (operands[0]) != MEM)
+  if (!MEM_P (operands[0]))
     {
       rtx stack_slot;
 
@@ -630,7 +630,7 @@ DIVU %1,%1,%2\;GET %0,:rR\;NEGU %2,0,%0\;CSNN %0,$255,%2")
   ""
   "
 {
-  if (GET_CODE (operands[0]) != MEM)
+  if (!MEM_P (operands[0]))
     {
       /* FIXME: There should be a way to say: 'put this in operands[0]
 	 but *after* the expanded insn'.  */
@@ -665,7 +665,7 @@ DIVU %1,%1,%2\;GET %0,:rR\;NEGU %2,0,%0\;CSNN %0,$255,%2")
   ""
   "
 {
-  if (GET_CODE (operands[1]) != MEM)
+  if (!MEM_P (operands[1]))
     {
       rtx stack_slot;
 
diff --git a/gcc/config/msp430/msp430.c b/gcc/config/msp430/msp430.c
index 40796b45883..0d3421a0121 100644
--- a/gcc/config/msp430/msp430.c
+++ b/gcc/config/msp430/msp430.c
@@ -3168,7 +3168,7 @@ msp430_fixup_compare_operands (machine_mode my_mode, rtx * operands)
     const_op_idx = 2;
 
   if (!REG_P (operands[const_op_idx])
-      && GET_CODE (operands[const_op_idx]) != MEM)
+      && !MEM_P (operands[const_op_idx]))
     operands[const_op_idx] = copy_to_mode_reg (my_mode, operands[const_op_idx]);
 }
 
@@ -3194,7 +3194,7 @@ msp430_subreg (machine_mode mode, rtx r, machine_mode omode, int byte)
       else
 	rv = simplify_gen_subreg (mode, ireg, imode, byte);
     }
-  else if (GET_CODE (r) == MEM)
+  else if (MEM_P (r))
     rv = adjust_address (r, mode, byte);
   else if (GET_CODE (r) == SYMBOL_REF
 	   && (byte == 0 || byte == 2)
diff --git a/gcc/config/nds32/nds32-fp-as-gp.c b/gcc/config/nds32/nds32-fp-as-gp.c
index b8b038aaa7a..6b5b84fa3d8 100644
--- a/gcc/config/nds32/nds32-fp-as-gp.c
+++ b/gcc/config/nds32/nds32-fp-as-gp.c
@@ -84,7 +84,7 @@ nds32_get_symbol_count (void)
 		 so don't count any other than SImode.
 		 MEM for QImode and HImode will wrap by ZERO_EXTEND
 		 or SIGN_EXTEND */
-	      if (GET_CODE (mem) == MEM)
+	      if (MEM_P (mem))
 		symbol_count++;
 	    }
 	}
diff --git a/gcc/config/nds32/nds32-multiple.md b/gcc/config/nds32/nds32-multiple.md
index 7a767e7e426..96fae88d2cf 100644
--- a/gcc/config/nds32/nds32-multiple.md
+++ b/gcc/config/nds32/nds32-multiple.md
@@ -60,7 +60,7 @@
       || INTVAL (operands[2]) > maximum
       || INTVAL (operands[2]) < 2
       || !REG_P (operands[0])
-      || GET_CODE (operands[1]) != MEM
+      || !MEM_P (operands[1])
       || MEM_VOLATILE_P (operands[1])
       || REGNO (operands[0]) + INTVAL (operands[2]) > TA_REGNUM)
     FAIL;
@@ -1908,7 +1908,7 @@
   if (!CONST_INT_P (operands[2])
       || INTVAL (operands[2]) > maximum
       || INTVAL (operands[2]) < 2
-      || GET_CODE (operands[0]) != MEM
+      || !MEM_P (operands[0])
       || !REG_P (operands[1])
       || MEM_VOLATILE_P (operands[0])
       || REGNO (operands[1]) + INTVAL (operands[2]) > TA_REGNUM)
diff --git a/gcc/config/nds32/nds32-predicates.c b/gcc/config/nds32/nds32-predicates.c
index 649b34d3c5b..7cfa77eb5cd 100644
--- a/gcc/config/nds32/nds32-predicates.c
+++ b/gcc/config/nds32/nds32-predicates.c
@@ -76,7 +76,7 @@ nds32_consecutive_registers_load_store_p (rtx op,
       if (!REG_P (elt_reg) || GET_MODE (elt_reg) != SImode)
 	return false;
       /* If elt_mem is not a expected mem rtx, return false.  */
-      if (GET_CODE (elt_mem) != MEM || GET_MODE (elt_mem) != SImode)
+      if (!MEM_P (elt_mem) || GET_MODE (elt_mem) != SImode)
 	return false;
 
       /* The consecutive registers should be in (Rb,Rb+1...Re) order.  */
@@ -136,7 +136,7 @@ nds32_valid_multiple_load_store_p (rtx op, bool load_p, bool bim_p)
   if (load_p)
     {
       if (!REG_P (SET_DEST (elt))
-	  || GET_CODE (SET_SRC (elt)) != MEM)
+	  || !MEM_P (SET_SRC (elt)))
 	return false;
 
       first_elt_regno = REGNO (SET_DEST (elt));
@@ -144,7 +144,7 @@ nds32_valid_multiple_load_store_p (rtx op, bool load_p, bool bim_p)
   else
     {
       if (!REG_P (SET_SRC (elt))
-	  || GET_CODE (SET_DEST (elt)) != MEM)
+	  || !MEM_P (SET_DEST (elt)))
 	return false;
 
       first_elt_regno = REGNO (SET_SRC (elt));
@@ -302,7 +302,7 @@ nds32_valid_stack_push_pop_p (rtx op, bool push_p)
       elt_reg = push_p ? SET_SRC (elt) : SET_DEST (elt);
       index++;
 
-      if (GET_CODE (elt_mem) != MEM
+      if (!MEM_P (elt_mem)
 	  || !REG_P (elt_reg)
 	  || REGNO (elt_reg) != FP_REGNUM)
 	return false;
@@ -314,7 +314,7 @@ nds32_valid_stack_push_pop_p (rtx op, bool push_p)
       elt_reg = push_p ? SET_SRC (elt) : SET_DEST (elt);
       index++;
 
-      if (GET_CODE (elt_mem) != MEM
+      if (!MEM_P (elt_mem)
 	  || !REG_P (elt_reg)
 	  || REGNO (elt_reg) != GP_REGNUM)
 	return false;
@@ -326,7 +326,7 @@ nds32_valid_stack_push_pop_p (rtx op, bool push_p)
       elt_reg = push_p ? SET_SRC (elt) : SET_DEST (elt);
       index++;
 
-      if (GET_CODE (elt_mem) != MEM
+      if (!MEM_P (elt_mem)
 	  || !REG_P (elt_reg)
 	  || REGNO (elt_reg) != LP_REGNUM)
 	return false;
diff --git a/gcc/config/nios2/nios2.c b/gcc/config/nios2/nios2.c
index 74c80bbd1e3..6378b7567a5 100644
--- a/gcc/config/nios2/nios2.c
+++ b/gcc/config/nios2/nios2.c
@@ -2253,7 +2253,7 @@ nios2_large_constant_memory_operand_p (rtx x)
 {
   rtx addr;
 
-  if (GET_CODE (x) != MEM)
+  if (!MEM_P (x))
     return false;
   addr = XEXP (x, 0);
 
@@ -2904,7 +2904,7 @@ nios2_print_operand (FILE *file, rtx op, int letter)
       return;
 
     case 'o':
-      if (GET_CODE (op) == MEM
+      if (MEM_P (op)
 	  && ((MEM_VOLATILE_P (op) && TARGET_BYPASS_CACHE_VOLATILE)
 	      || TARGET_BYPASS_CACHE))
 	{
diff --git a/gcc/config/nvptx/nvptx.c b/gcc/config/nvptx/nvptx.c
index 39050c5e492..dd3b14c515a 100644
--- a/gcc/config/nvptx/nvptx.c
+++ b/gcc/config/nvptx/nvptx.c
@@ -2500,7 +2500,7 @@ nvptx_print_address_operand (FILE *file, rtx x, machine_mode)
       break;
 
     default:
-      gcc_assert (GET_CODE (x) != MEM);
+      gcc_assert (!MEM_P (x));
       nvptx_print_operand (file, x, 0);
       break;
     }
@@ -2907,7 +2907,7 @@ nvptx_call_insn_is_syscall_p (rtx_insn *insn)
   if (GET_CODE (pat) == SET)
     pat = SET_SRC (pat);
   gcc_checking_assert (GET_CODE (pat) == CALL
-		       && GET_CODE (XEXP (pat, 0)) == MEM);
+		       && MEM_P (XEXP (pat, 0)));
   rtx addr = XEXP (XEXP (pat, 0), 0);
   if (GET_CODE (addr) != SYMBOL_REF)
     return false;
diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c
index cdd2e031bf7..1df00c00dbf 100644
--- a/gcc/config/pa/pa.c
+++ b/gcc/config/pa/pa.c
@@ -1640,7 +1640,7 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
   /* We can only handle indexed addresses in the destination operand
      of floating point stores.  Thus, we need to break out indexed
      addresses from the destination operand.  */
-  if (GET_CODE (operand0) == MEM && IS_INDEX_ADDR_P (XEXP (operand0, 0)))
+  if (MEM_P (operand0) && IS_INDEX_ADDR_P (XEXP (operand0, 0)))
     {
       gcc_assert (can_create_pseudo_p ());
 
@@ -1657,7 +1657,7 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
      unscaled indexed addresses.  */
   if (!TARGET_NO_SPACE_REGS
       && !cse_not_expected
-      && GET_CODE (operand1) == MEM
+      && MEM_P (operand1)
       && GET_CODE (XEXP (operand1, 0)) == PLUS
       && REG_P (XEXP (XEXP (operand1, 0), 0))
       && REG_P (XEXP (XEXP (operand1, 0), 1)))
@@ -1699,12 +1699,12 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
       operand1 = alter_subreg (&temp, true);
     }
 
-  if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
+  if (scratch_reg && reload_in_progress && MEM_P (operand0)
       && ((tem = find_replacement (&XEXP (operand0, 0)))
 	  != XEXP (operand0, 0)))
     operand0 = replace_equiv_address (operand0, tem);
 
-  if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
+  if (scratch_reg && reload_in_progress && MEM_P (operand1)
       && ((tem = find_replacement (&XEXP (operand1, 0)))
 	  != XEXP (operand1, 0)))
     operand1 = replace_equiv_address (operand1, tem);
@@ -1855,11 +1855,11 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
 	   && REG_P (operand0)
 	   && REGNO (operand0) < FIRST_PSEUDO_REGISTER
 	   && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
-	   && (GET_CODE (operand1) == MEM || CONST_INT_P (operand1)))
+	   && (MEM_P (operand1) || CONST_INT_P (operand1)))
     {
       /* D might not fit in 14 bits either; for such cases load D into
 	 scratch reg.  */
-      if (GET_CODE (operand1) == MEM
+      if (MEM_P (operand1)
 	  && !memory_address_p (GET_MODE (operand0), XEXP (operand1, 0)))
 	{
 	  /* We are reloading the address into the scratch register, so we
@@ -1914,7 +1914,7 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
 	  || (GET_CODE (operand1) == HIGH
 	      && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
 	  /* Only `general_operands' can come here, so MEM is ok.  */
-	  || GET_CODE (operand1) == MEM)
+	  || MEM_P (operand1))
 	{
 	  /* Various sets are created during RTL generation which don't
 	     have the REG_POINTER flag correctly set.  After the CSE pass,
@@ -1934,7 +1934,7 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
 	     get set.  In some cases, we can set the REG_POINTER flag
 	     from the declaration for the MEM.  */
 	  if (REG_P (operand0)
-	      && GET_CODE (operand1) == MEM
+	      && MEM_P (operand1)
 	      && !REG_POINTER (operand0))
 	    {
 	      tree decl = MEM_EXPR (operand1);
@@ -1963,7 +1963,7 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
 	  return 1;
 	}
     }
-  else if (GET_CODE (operand0) == MEM)
+  else if (MEM_P (operand0))
     {
       if (mode == DFmode && operand1 == CONST0_RTX (mode)
 	  && !(reload_in_progress || reload_completed))
@@ -2380,9 +2380,9 @@ pa_singlemove_string (rtx *operands)
 {
   HOST_WIDE_INT intval;
 
-  if (GET_CODE (operands[0]) == MEM)
+  if (MEM_P (operands[0]))
     return "stw %r1,%0";
-  if (GET_CODE (operands[1]) == MEM)
+  if (MEM_P (operands[1]))
     return "ldw %1,%0";
   if (CONST_DOUBLE_P (operands[1]))
     {
@@ -2512,7 +2512,7 @@ pa_output_move_double (rtx *operands)
     optype0 = REGOP;
   else if (offsettable_memref_p (operands[0]))
     optype0 = OFFSOP;
-  else if (GET_CODE (operands[0]) == MEM)
+  else if (MEM_P (operands[0]))
     optype0 = MEMOP;
   else
     optype0 = RNDOP;
@@ -2523,7 +2523,7 @@ pa_output_move_double (rtx *operands)
     optype1 = CNSTOP;
   else if (offsettable_memref_p (operands[1]))
     optype1 = OFFSOP;
-  else if (GET_CODE (operands[1]) == MEM)
+  else if (MEM_P (operands[1]))
     optype1 = MEMOP;
   else
     optype1 = RNDOP;
@@ -5056,8 +5056,8 @@ pa_adjust_insn_length (rtx_insn *insn, int length)
   if (NONJUMP_INSN_P (insn)
       && GET_CODE (pat) == PARALLEL
       && GET_CODE (XVECEXP (pat, 0, 0)) == SET
-      && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
-      && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
+      && MEM_P (XEXP (XVECEXP (pat, 0, 0), 0))
+      && MEM_P (XEXP (XVECEXP (pat, 0, 0), 1))
       && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
       && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
     length += compute_cpymem_length (insn) - 4;
@@ -5065,7 +5065,7 @@ pa_adjust_insn_length (rtx_insn *insn, int length)
   else if (NONJUMP_INSN_P (insn)
 	   && GET_CODE (pat) == PARALLEL
 	   && GET_CODE (XVECEXP (pat, 0, 0)) == SET
-	   && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
+	   && MEM_P (XEXP (XVECEXP (pat, 0, 0), 0))
 	   && XEXP (XVECEXP (pat, 0, 0), 1) == const0_rtx
 	   && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode)
     length += compute_clrmem_length (insn) - 4;
@@ -5437,7 +5437,7 @@ pa_print_operand (FILE *file, rtx x, int code)
 	  && (REGNO (x) & 1) == 0)
 	fputs ("L", file);
     }
-  else if (GET_CODE (x) == MEM)
+  else if (MEM_P (x))
     {
       int size = GET_MODE_SIZE (GET_MODE (x));
       rtx base = NULL_RTX;
@@ -6046,7 +6046,7 @@ pa_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
   /* If we have something like (mem (mem (...)), we can safely assume the
      inner MEM will end up in a general register after reloading, so there's
      no need for a secondary reload.  */
-  if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == MEM)
+  if (MEM_P (x) && MEM_P (XEXP (x, 0)))
     return NO_REGS;
 
   /* Trying to load a constant into a FP register during PIC code
diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 01c778368cd..f0e498e2782 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -3269,9 +3269,9 @@
 	      (use (match_operand:SI 4 "arith14_operand" ""))
 	      (use (match_operand:SI 5 "const_int_operand" ""))])]
   "!TARGET_64BIT && reload_completed && !flag_peephole2
-   && GET_CODE (operands[0]) == MEM
+   && MEM_P (operands[0])
    && register_operand (XEXP (operands[0], 0), SImode)
-   && GET_CODE (operands[1]) == MEM
+   && MEM_P (operands[1])
    && register_operand (XEXP (operands[1], 0), SImode)"
   [(set (match_dup 7) (match_dup 9))
    (set (match_dup 8) (match_dup 10))
@@ -3303,9 +3303,9 @@
 	      (use (match_operand:SI 4 "arith14_operand" ""))
 	      (use (match_operand:SI 5 "const_int_operand" ""))])]
   "!TARGET_64BIT
-   && GET_CODE (operands[0]) == MEM
+   && MEM_P (operands[0])
    && register_operand (XEXP (operands[0], 0), SImode)
-   && GET_CODE (operands[1]) == MEM
+   && MEM_P (operands[1])
    && register_operand (XEXP (operands[1], 0), SImode)"
   [(parallel [(set (match_dup 0) (match_dup 1))
    	      (clobber (match_dup 2))
@@ -3457,9 +3457,9 @@
 	      (use (match_operand:DI 4 "arith14_operand" ""))
 	      (use (match_operand:DI 5 "const_int_operand" ""))])]
   "TARGET_64BIT && reload_completed && !flag_peephole2
-   && GET_CODE (operands[0]) == MEM
+   && MEM_P (operands[0])
    && register_operand (XEXP (operands[0], 0), DImode)
-   && GET_CODE (operands[1]) == MEM
+   && MEM_P (operands[1])
    && register_operand (XEXP (operands[1], 0), DImode)"
   [(set (match_dup 7) (match_dup 9))
    (set (match_dup 8) (match_dup 10))
@@ -3491,9 +3491,9 @@
 	      (use (match_operand:DI 4 "arith14_operand" ""))
 	      (use (match_operand:DI 5 "const_int_operand" ""))])]
   "TARGET_64BIT
-   && GET_CODE (operands[0]) == MEM
+   && MEM_P (operands[0])
    && register_operand (XEXP (operands[0], 0), DImode)
-   && GET_CODE (operands[1]) == MEM
+   && MEM_P (operands[1])
    && register_operand (XEXP (operands[1], 0), DImode)"
   [(parallel [(set (match_dup 0) (match_dup 1))
    	      (clobber (match_dup 2))
@@ -3599,7 +3599,7 @@
 	      (use (match_operand:SI 2 "arith14_operand" ""))
 	      (use (match_operand:SI 3 "const_int_operand" ""))])]
   "!TARGET_64BIT && reload_completed && !flag_peephole2
-   && GET_CODE (operands[0]) == MEM
+   && MEM_P (operands[0])
    && register_operand (XEXP (operands[0], 0), SImode)"
   [(set (match_dup 4) (match_dup 5))
    (parallel [(set (match_dup 0) (const_int 0))
@@ -3622,7 +3622,7 @@
 	      (use (match_operand:SI 2 "arith14_operand" ""))
 	      (use (match_operand:SI 3 "const_int_operand" ""))])]
   "!TARGET_64BIT
-   && GET_CODE (operands[0]) == MEM
+   && MEM_P (operands[0])
    && register_operand (XEXP (operands[0], 0), SImode)"
   [(parallel [(set (match_dup 0) (const_int 0))
    	      (clobber (match_dup 1))
@@ -3713,7 +3713,7 @@
 	      (use (match_operand:DI 2 "arith14_operand" ""))
 	      (use (match_operand:DI 3 "const_int_operand" ""))])]
   "TARGET_64BIT && reload_completed && !flag_peephole2
-   && GET_CODE (operands[0]) == MEM
+   && MEM_P (operands[0])
    && register_operand (XEXP (operands[0], 0), DImode)"
   [(set (match_dup 4) (match_dup 5))
    (parallel [(set (match_dup 0) (const_int 0))
@@ -3736,7 +3736,7 @@
 	      (use (match_operand:DI 2 "arith14_operand" ""))
 	      (use (match_operand:DI 3 "const_int_operand" ""))])]
   "TARGET_64BIT
-   && GET_CODE (operands[0]) == MEM
+   && MEM_P (operands[0])
    && register_operand (XEXP (operands[0], 0), DImode)"
   [(parallel [(set (match_dup 0) (const_int 0))
    	      (clobber (match_dup 1))
@@ -3838,7 +3838,7 @@
   "(register_operand (operands[0], DFmode)
     || reg_or_0_operand (operands[1], DFmode))
    && !(CONST_DOUBLE_P (operands[1])
-	&& GET_CODE (operands[0]) == MEM)
+	&& MEM_P (operands[0]))
    && !TARGET_64BIT
    && !TARGET_SOFT_FLOAT"
   "*
diff --git a/gcc/config/pdp11/pdp11.c b/gcc/config/pdp11/pdp11.c
index 7a3e24a1b1f..53211af53f7 100644
--- a/gcc/config/pdp11/pdp11.c
+++ b/gcc/config/pdp11/pdp11.c
@@ -490,16 +490,16 @@ pdp11_expand_operands (rtx *operands, rtx exops[][2],
   useorder = either;
   if (opcount == 2)
     {
-      if (GET_CODE (operands[0]) == MEM &&
-	  GET_CODE (operands[1]) == MEM &&
+      if (MEM_P (operands[0]) &&
+	  MEM_P (operands[1]) &&
 	  ((GET_CODE (XEXP (operands[0], 0)) == POST_INC &&
 	    GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) ||
 	   (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC &&
 	    GET_CODE (XEXP (operands[1], 0)) == POST_INC)))
 	    useorder = big;
-      else if ((GET_CODE (operands[0]) == MEM &&
+      else if ((MEM_P (operands[0]) &&
 		GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) ||
-	       (GET_CODE (operands[1]) == MEM &&
+	       (MEM_P (operands[1]) &&
 		GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))
 	useorder = little;
       else if (REG_P (operands[0]) && REG_P (operands[1]) &&
@@ -545,7 +545,7 @@ pdp11_expand_operands (rtx *operands, rtx exops[][2],
 	optype = PUSHOP;
       else if (!reload_in_progress || offsettable_memref_p (operands[op]))
 	optype = OFFSOP;
-      else if (GET_CODE (operands[op]) == MEM)
+      else if (MEM_P (operands[op]))
 	optype = MEMOP;
       else
 	optype = RNDOP;
@@ -799,7 +799,7 @@ pdp11_asm_print_operand (FILE *file, rtx x, int code)
     }
   else if (REG_P (x))
     fprintf (file, "%s", reg_names[REGNO (x)]);
-  else if (GET_CODE (x) == MEM)
+  else if (MEM_P (x))
     output_address (GET_MODE (x), XEXP (x, 0));
   else if (CONST_DOUBLE_P (x) && FLOAT_MODE_P (GET_MODE (x)))
     {
@@ -866,13 +866,13 @@ print_operand_address (FILE *file, register rtx addr)
       breg = 0;
       offset = 0;
       if (CONSTANT_ADDRESS_P (XEXP (addr, 0))
-	  || GET_CODE (XEXP (addr, 0)) == MEM)
+	  || MEM_P (XEXP (addr, 0)))
 	{
 	  offset = XEXP (addr, 0);
 	  addr = XEXP (addr, 1);
 	}
       else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))
-	       || GET_CODE (XEXP (addr, 1)) == MEM)
+	       || MEM_P (XEXP (addr, 1)))
 	{
 	  offset = XEXP (addr, 1);
 	  addr = XEXP (addr, 0);
@@ -1349,7 +1349,7 @@ simple_memory_operand(rtx op, machine_mode mode ATTRIBUTE_UNUSED)
   rtx addr;
 
   /* Eliminate non-memory operations */
-  if (GET_CODE (op) != MEM)
+  if (!MEM_P (op))
     return FALSE;
 
   /* Decode the address now.  */
@@ -1407,7 +1407,7 @@ no_side_effect_operand(rtx op, machine_mode mode ATTRIBUTE_UNUSED)
   rtx addr;
 
   /* Eliminate non-memory operations */
-  if (GET_CODE (op) != MEM)
+  if (!MEM_P (op))
     return FALSE;
 
   /* Decode the address now.  */
@@ -1464,13 +1464,13 @@ pushpop_regeq (rtx op, int regno)
   rtx addr;
   
   /* False if not memory reference.  */
-  if (GET_CODE (op) != MEM)
+  if (!MEM_P (op))
     return FALSE;
   
   /* Get the address of the memory reference.  */
   addr = XEXP (op, 0);
 
-  if (GET_CODE (addr) == MEM)
+  if (MEM_P (addr))
     addr = XEXP (addr, 0);
     
   switch (GET_CODE (addr))
diff --git a/gcc/config/pru/predicates.md b/gcc/config/pru/predicates.md
index eae67483f63..adead56621b 100644
--- a/gcc/config/pru/predicates.md
+++ b/gcc/config/pru/predicates.md
@@ -199,7 +199,7 @@
   /* Perform a quick check so we don't blow up below.  */
   if (GET_CODE (XVECEXP (op, 0, 0)) != SET
       || !REG_P (SET_DEST (XVECEXP (op, 0, 0)))
-      || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
+      || !MEM_P (SET_SRC (XVECEXP (op, 0, 0))))
     return false;
 
   dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
@@ -220,7 +220,7 @@
 	  || !REG_P (SET_DEST (elt))
 	  || GET_MODE (SET_DEST (elt)) != elt_mode
 	  || REGNO (SET_DEST (elt)) != dest_regno + i * GET_MODE_SIZE (elt_mode)
-	  || GET_CODE (SET_SRC (elt)) != MEM
+	  || !MEM_P (SET_SRC (elt))
 	  || GET_MODE (SET_SRC (elt)) != elt_mode)
 	return false;
 
@@ -250,7 +250,7 @@
 
   /* Perform a quick check so we don't blow up below.  */
   if (GET_CODE (XVECEXP (op, 0, 0)) != SET
-      || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
+      || !MEM_P (SET_DEST (XVECEXP (op, 0, 0)))
       || !REG_P (SET_SRC (XVECEXP (op, 0, 0))))
     return false;
 
@@ -272,7 +272,7 @@
 	  || !REG_P (SET_SRC (elt))
 	  || GET_MODE (SET_SRC (elt)) != elt_mode
 	  || REGNO (SET_SRC (elt)) != src_regno + i * GET_MODE_SIZE (elt_mode)
-	  || GET_CODE (SET_DEST (elt)) != MEM
+	  || !MEM_P (SET_DEST (elt))
 	  || GET_MODE (SET_DEST (elt)) != elt_mode)
 	return false;
 
diff --git a/gcc/config/pru/pru.md b/gcc/config/pru/pru.md
index c1cb98f5001..4e500d5ea13 100644
--- a/gcc/config/pru/pru.md
+++ b/gcc/config/pru/pru.md
@@ -231,7 +231,7 @@
   /* Support only loading a constant number of fixed-point registers from
      memory.  */
   if (!CONST_INT_P (operands[2])
-      || GET_CODE (operands[1]) != MEM
+      || !MEM_P (operands[1])
       || !REG_P (operands[0]))
     FAIL;
 
@@ -289,7 +289,7 @@
   /* Support only storing a constant number of fixed-point registers to
      memory.  */
   if (!CONST_INT_P (operands[2])
-      || GET_CODE (operands[0]) != MEM
+      || !MEM_P (operands[0])
       || !REG_P (operands[1]))
     FAIL;
 
diff --git a/gcc/config/rl78/rl78.c b/gcc/config/rl78/rl78.c
index 779c94e038f..a667ac8f543 100644
--- a/gcc/config/rl78/rl78.c
+++ b/gcc/config/rl78/rl78.c
@@ -522,7 +522,7 @@ rl78_modes_tieable_p (machine_mode mode1, machine_mode mode2)
 static rtx
 rl78_subreg (machine_mode mode, rtx r, machine_mode omode, int byte)
 {
-  if (GET_CODE (r) == MEM)
+  if (MEM_P (r))
     return adjust_address (r, mode, byte);
   else
     return simplify_gen_subreg (mode, r, omode, byte);
@@ -2233,7 +2233,7 @@ rl78_trampoline_adjust_address (rtx m_tramp)
 void
 rl78_expand_compare (rtx *operands)
 {
-  if (GET_CODE (operands[2]) == MEM)
+  if (MEM_P (operands[2]))
     operands[2] = copy_to_mode_reg (GET_MODE (operands[2]), operands[2]);
 }
 
@@ -2268,7 +2268,7 @@ rl78_peep_movhi_p (rtx *operands)
 #endif
 
   /* You can move a constant to memory as QImode, but not HImode.  */
-  if (GET_CODE (operands[0]) == MEM
+  if (MEM_P (operands[0])
       && !REG_P (operands[1]))
     {
 #if DEBUG_PEEP
@@ -2688,7 +2688,7 @@ already_contains (rtx loc, rtx value)
 bool
 rl78_es_addr (rtx addr)
 {
-  if (GET_CODE (addr) == MEM)
+  if (MEM_P (addr))
     addr = XEXP (addr, 0);
   if (GET_CODE (addr) != UNSPEC)
     return false;
@@ -2700,7 +2700,7 @@ rl78_es_addr (rtx addr)
 rtx
 rl78_es_base (rtx addr)
 {
-  if (GET_CODE (addr) == MEM)
+  if (MEM_P (addr))
     addr = XEXP (addr, 0);
   addr = XVECEXP (addr, 0, 1);
   if (GET_CODE (addr) == CONST
@@ -2737,7 +2737,7 @@ insn_ok_now (rtx_insn * insn)
 	  /* We need to detect far addresses that haven't been
 	     converted to es/lo16 format.  */
 	  for (i=0; i<recog_data.n_operands; i++)
-	    if (GET_CODE (OP (i)) == MEM
+	    if (MEM_P (OP (i))
 		&& GET_MODE (XEXP (OP (i), 0)) == SImode
 		&& GET_CODE (XEXP (OP (i), 0)) != UNSPEC)
 	      goto not_ok;
@@ -3901,7 +3901,7 @@ rl78_note_reg_set (char *dead, rtx d, rtx insn)
 {
   int r, i;
   bool is_dead;
-  if (GET_CODE (d) == MEM)
+  if (MEM_P (d))
     rl78_note_reg_uses (dead, XEXP (d, 0), insn);
 
   if (!REG_P (d))
@@ -4567,7 +4567,7 @@ rl78_encode_section_info (tree decl, rtx rtl, int first)
 
   if (GET_CODE (rtlname) == SYMBOL_REF)
     oldname = XSTR (rtlname, 0);
-  else if (GET_CODE (rtlname) == MEM
+  else if (MEM_P (rtlname)
 	   && GET_CODE (XEXP (rtlname, 0)) == SYMBOL_REF)
     oldname = XSTR (XEXP (rtlname, 0), 0);
   else
diff --git a/gcc/config/rx/rx.c b/gcc/config/rx/rx.c
index ea04eb6b836..e529f8b173e 100644
--- a/gcc/config/rx/rx.c
+++ b/gcc/config/rx/rx.c
@@ -80,7 +80,7 @@ rx_pid_base_regnum (void)
 static tree
 rx_decl_for_addr (rtx op)
 {
-  if (GET_CODE (op) == MEM)
+  if (MEM_P (op))
     op = XEXP (op, 0);
   if (GET_CODE (op) == CONST)
     op = XEXP (op, 0);
@@ -940,7 +940,7 @@ rx_maybe_pidify_operand (rtx op, int copy_to_reg)
 {
   if (rx_pid_data_operand (op) == PID_UNENCODED)
     {
-      if (GET_CODE (op) == MEM)
+      if (MEM_P (op))
 	{
 	  rtx a = gen_pid_addr (gen_rtx_REG (SImode, rx_pid_base_regnum ()), XEXP (op, 0));
 	  op = replace_equiv_address (op, a);
diff --git a/gcc/config/s390/predicates.md b/gcc/config/s390/predicates.md
index b05e8ed6ed0..e7ce44dbb43 100644
--- a/gcc/config/s390/predicates.md
+++ b/gcc/config/s390/predicates.md
@@ -66,10 +66,10 @@
      after reload.  */
   if (reload_completed
       && SUBREG_P (op)
-      && GET_CODE (SUBREG_REG (op)) == MEM)
+      && MEM_P (SUBREG_REG (op)))
     op = SUBREG_REG (op);
 
-  if (GET_CODE (op) != MEM)
+  if (!MEM_P (op))
     return false;
   if (!s390_legitimate_address_without_index_p (op))
     return false;
@@ -394,7 +394,7 @@
   if (count <= 1
       || GET_CODE (XVECEXP (op, 0, 0)) != SET
       || !REG_P (SET_DEST (XVECEXP (op, 0, 0)))
-      || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
+      || !MEM_P (SET_SRC (XVECEXP (op, 0, 0))))
     return false;
 
   dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
@@ -423,7 +423,7 @@
 	  || !REG_P (SET_DEST (elt))
 	  || GET_MODE (SET_DEST (elt)) != elt_mode
 	  || REGNO (SET_DEST (elt)) != dest_regno + i
-	  || GET_CODE (SET_SRC (elt)) != MEM
+	  || !MEM_P (SET_SRC (elt))
 	  || GET_MODE (SET_SRC (elt)) != elt_mode
 	  || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
 	  || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
@@ -496,7 +496,7 @@
   /* Perform a quick check so we don't blow up below.  */
   if (count <= 1
       || GET_CODE (XVECEXP (op, 0, 0)) != SET
-      || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
+      || !MEM_P (SET_DEST (XVECEXP (op, 0, 0)))
       || !REG_P (SET_SRC (XVECEXP (op, 0, 0))))
     return false;
 
@@ -526,7 +526,7 @@
 	  || !REG_P (SET_SRC (elt))
 	  || GET_MODE (SET_SRC (elt)) != elt_mode
 	  || REGNO (SET_SRC (elt)) != src_regno + i
-	  || GET_CODE (SET_DEST (elt)) != MEM
+	  || !MEM_P (SET_DEST (elt))
 	  || GET_MODE (SET_DEST (elt)) != elt_mode
 	  || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
 	  || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index d38cf3aad12..acec764bc42 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -2562,8 +2562,8 @@ s390_split_ok_p (rtx dst, rtx src, machine_mode mode, int first_subword)
     return false;
 
   /* Non-offsettable memory references cannot be split.  */
-  if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
-      || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
+  if ((MEM_P (src) && !offsettable_memref_p (src))
+      || (MEM_P (dst) && !offsettable_memref_p (dst)))
     return false;
 
   /* Moving the first subword must not clobber a register
@@ -2588,7 +2588,7 @@ s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
   rtx addr1, addr2, addr_delta;
   HOST_WIDE_INT delta;
 
-  if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
+  if (!MEM_P (mem1) || !MEM_P (mem2))
     return true;
 
   if (size == 0)
@@ -2629,7 +2629,7 @@ s390_offset_p (rtx mem1, rtx mem2, rtx delta)
 {
   rtx addr1, addr2, addr_delta;
 
-  if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
+  if (!MEM_P (mem1) || !MEM_P (mem2))
     return false;
 
   addr1 = XEXP (mem1, 0);
@@ -2660,7 +2660,7 @@ s390_expand_logical_operator (enum rtx_code code, machine_mode mode,
 
   /* QImode and HImode patterns make sense only if we have a destination
      in memory.  Otherwise perform the operation in SImode.  */
-  if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
+  if ((mode == QImode || mode == HImode) && !MEM_P (dst))
     wmode = SImode;
 
   /* Widen operands if required.  */
@@ -2705,7 +2705,7 @@ s390_logical_operator_ok_p (rtx *operands)
   /* If the destination operand is in memory, it needs to coincide
      with one of the source operands.  After reload, it has to be
      the first source operand.  */
-  if (GET_CODE (operands[0]) == MEM)
+  if (MEM_P (operands[0]))
     return rtx_equal_p (operands[0], operands[1])
 	   || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
 
@@ -2722,7 +2722,7 @@ s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
   HOST_WIDE_INT mask;
   int part;
 
-  gcc_assert (GET_CODE (*memop) == MEM);
+  gcc_assert (MEM_P (*memop));
   gcc_assert (!MEM_VOLATILE_P (*memop));
 
   mask = s390_extract_part (*immop, QImode, def);
@@ -3359,7 +3359,7 @@ s390_mem_constraint (const char *str, rtx op)
     case 'R':
     case 'S':
     case 'T':
-      if (GET_CODE (op) != MEM)
+      if (!MEM_P (op))
 	return 0;
       return s390_check_qrst_address (c, XEXP (op, 0), true);
     case 'Y':
@@ -5292,7 +5292,7 @@ emit_symbolic_move (rtx *operands)
 {
   rtx temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
 
-  if (GET_CODE (operands[0]) == MEM)
+  if (MEM_P (operands[0]))
     operands[1] = force_reg (Pmode, operands[1]);
   else if (TLS_SYMBOLIC_CONST (operands[1]))
     operands[1] = legitimize_tls_address (operands[1], temp);
@@ -7429,7 +7429,7 @@ s390_delegitimize_address (rtx orig_x)
 	return plus_constant (Pmode, XVECEXP (y, 0, 0), offset);
     }
 
-  if (GET_CODE (x) != MEM)
+  if (!MEM_P (x))
     return orig_x;
 
   x = XEXP (x, 0);
@@ -7966,7 +7966,7 @@ print_operand (FILE *file, rtx x, int code)
     case 'N':
       if (REG_P (x))
 	x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
-      else if (GET_CODE (x) == MEM)
+      else if (MEM_P (x))
 	x = change_address (x, VOIDmode,
 			    plus_constant (Pmode, XEXP (x, 0), 4));
       else
@@ -7977,7 +7977,7 @@ print_operand (FILE *file, rtx x, int code)
     case 'M':
       if (REG_P (x))
 	x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
-      else if (GET_CODE (x) == MEM)
+      else if (MEM_P (x))
 	x = change_address (x, VOIDmode,
 			    plus_constant (Pmode, XEXP (x, 0), 8));
       else
@@ -8332,7 +8332,7 @@ annotate_constant_pool_refs_1 (rtx *x)
 	      || !CONSTANT_POOL_ADDRESS_P (*x));
 
   /* Literal pool references can only occur inside a MEM ...  */
-  if (GET_CODE (*x) == MEM)
+  if (MEM_P (*x))
     {
       rtx memref = XEXP (*x, 0);
 
@@ -9464,7 +9464,7 @@ s390_regs_ever_clobbered (char regs_ever_clobbered[])
 		    continue;
 
 		  /* l / lg  */
-		  if (GET_CODE (SET_SRC (pat)) == MEM)
+		  if (MEM_P (SET_SRC (pat)))
 		    continue;
 		}
 
@@ -13742,7 +13742,7 @@ s390_optimize_prologue (void)
       if (cfun_frame_layout.first_save_gpr == -1
 	  && GET_CODE (pat) == SET
 	  && GENERAL_REG_P (SET_SRC (pat))
-	  && GET_CODE (SET_DEST (pat)) == MEM)
+	  && MEM_P (SET_DEST (pat)))
 	{
 	  set = pat;
 	  first = REGNO (SET_SRC (set));
@@ -13813,7 +13813,7 @@ s390_optimize_prologue (void)
       if (cfun_frame_layout.first_restore_gpr == -1
 	  && GET_CODE (pat) == SET
 	  && GENERAL_REG_P (SET_DEST (pat))
-	  && GET_CODE (SET_SRC (pat)) == MEM)
+	  && MEM_P (SET_SRC (pat)))
 	{
 	  set = pat;
 	  first = REGNO (SET_DEST (set));
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 0f2cc5a7752..3305d9fdf73 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -2258,7 +2258,7 @@
      always sign-extends (at least) to SImode.  */
   if (optimize && can_create_pseudo_p ()
       && register_operand (operands[0], VOIDmode)
-      && GET_CODE (operands[1]) == MEM)
+      && MEM_P (operands[1]))
     {
       rtx tmp = gen_reg_rtx (SImode);
       rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
@@ -2324,7 +2324,7 @@
      is just as fast as a QImode load.  */
   if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
       && register_operand (operands[0], VOIDmode)
-      && GET_CODE (operands[1]) == MEM)
+      && MEM_P (operands[1]))
     {
       rtx tmp = gen_reg_rtx (DImode);
       rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
@@ -2840,7 +2840,7 @@
   if (!CONST_INT_P (operands[2])
       || INTVAL (operands[2]) < 2
       || INTVAL (operands[2]) > 16
-      || GET_CODE (operands[1]) != MEM
+      || !MEM_P (operands[1])
       || !REG_P (operands[0])
       || REGNO (operands[0]) >= 16)
     FAIL;
@@ -2931,7 +2931,7 @@
   if (!CONST_INT_P (operands[2])
       || INTVAL (operands[2]) < 2
       || INTVAL (operands[2]) > 16
-      || GET_CODE (operands[0]) != MEM
+      || !MEM_P (operands[0])
       || !REG_P (operands[1])
       || REGNO (operands[1]) >= 16)
     FAIL;
@@ -7714,7 +7714,7 @@
    (clobber (reg:CC CC_REGNUM))]
   "!TARGET_ARCH13
    && ! reload_completed
-   && (GET_CODE (operands[0]) != MEM
+   && (!MEM_P (operands[0])
       /* Ensure that s390_logical_operator_ok_p will succeed even
 	 on the split xor if (b & a) is stored into a pseudo.  */
        || rtx_equal_p (operands[0], operands[2]))"
diff --git a/gcc/config/sparc/predicates.md b/gcc/config/sparc/predicates.md
index d947736e933..b1c2059dd43 100644
--- a/gcc/config/sparc/predicates.md
+++ b/gcc/config/sparc/predicates.md
@@ -415,7 +415,7 @@
     op = SUBREG_REG (op);
 
   /* Check for valid MEM forms.  */
-  if (GET_CODE (op) == MEM)
+  if (MEM_P (op))
     {
       /* Except when LRA is precisely working hard to make them valid
 	 and relying entirely on the constraints.  */
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 523f2851d31..f3f61bdb947 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -2224,7 +2224,7 @@ bool
 sparc_expand_move (machine_mode mode, rtx *operands)
 {
   /* Handle sets of MEM first.  */
-  if (GET_CODE (operands[0]) == MEM)
+  if (MEM_P (operands[0]))
     {
       /* 0 is a register (or a pair of registers) on SPARC.  */
       if (register_or_zero_operand (operands[1], mode))
@@ -3638,7 +3638,7 @@ emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands)
 	  if (TARGET_BUGGY_QP_LIB && i == 0)
 	    force_stack_temp = 1;
 
-	  if (GET_CODE (this_arg) == MEM
+	  if (MEM_P (this_arg)
 	      && ! force_stack_temp)
 	    {
 	      tree expr = MEM_EXPR (this_arg);
@@ -4504,7 +4504,7 @@ sparc_legitimate_address_p (machine_mode mode, rtx addr, bool strict)
 	   && !REG_P (rs2)
 	   && !SUBREG_P (rs2)
 	   && GET_CODE (rs2) != LO_SUM
-	   && GET_CODE (rs2) != MEM
+	   && !MEM_P (rs2)
 	   && !(GET_CODE (rs2) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs2))
 	   && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
 	   && (!CONST_INT_P (rs2) || SMALL_INT (rs2)))
@@ -5160,7 +5160,7 @@ mem_min_alignment (rtx mem, int desired)
   rtx addr, base, offset;
 
   /* If it's not a MEM we can't accept it.  */
-  if (GET_CODE (mem) != MEM)
+  if (!MEM_P (mem))
     return 0;
 
   /* Obviously...  */
@@ -9587,7 +9587,7 @@ sparc_print_operand (FILE *file, rtx x, int code)
 
     case 'f':
       /* Operand must be a MEM; write its address.  */
-      if (GET_CODE (x) != MEM)
+      if (!MEM_P (x))
 	output_operand_lossage ("invalid %%f operand");
       output_address (GET_MODE (x), XEXP (x, 0));
       return;
@@ -9619,7 +9619,7 @@ sparc_print_operand (FILE *file, rtx x, int code)
 
   if (REG_P (x))
     fputs (reg_names[REGNO (x)], file);
-  else if (GET_CODE (x) == MEM)
+  else if (MEM_P (x))
     {
       fputc ('[', file);
 	/* Poor Sun assembler doesn't understand absolute addressing.  */
@@ -10141,8 +10141,8 @@ hypersparc_adjust_cost (rtx_insn *insn, int dtype, rtx_insn *dep_insn,
 	  if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
 	    {
 	      if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
-		  || GET_CODE (SET_DEST (dep_pat)) != MEM
-		  || GET_CODE (SET_SRC (pat)) != MEM
+		  || !MEM_P (SET_DEST (dep_pat))
+		  || !MEM_P (SET_SRC (pat))
 		  || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
 				    XEXP (SET_SRC (pat), 0)))
 		return cost + 2;
@@ -13402,7 +13402,7 @@ sparc_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
      a paradoxical subreg in a float/fix conversion insn.  */
   if (FP_REG_CLASS_P (rclass)
       && (mode == HImode || mode == QImode)
-      && (GET_CODE (x) == MEM
+      && (MEM_P (x)
 	  || ((REG_P (x) || SUBREG_P (x))
 	      && true_regnum (x) == -1)))
     return GENERAL_REGS;
@@ -13412,7 +13412,7 @@ sparc_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
   if (TARGET_ARCH32
       && rclass == EXTRA_FP_REGS
       && mode == DFmode
-      && GET_CODE (x) == MEM
+      && MEM_P (x)
       && ! mem_min_alignment (x, 8))
     return FP_REGS;
 
diff --git a/gcc/config/spu/spu.c b/gcc/config/spu/spu.c
index 668a1950c9a..4527842e8b6 100644
--- a/gcc/config/spu/spu.c
+++ b/gcc/config/spu/spu.c
@@ -482,7 +482,7 @@ spu_expand_insv (rtx ops[])
   int shift;
 
 
-  if (GET_CODE (ops[0]) == MEM)
+  if (MEM_P (ops[0]))
     dst = gen_reg_rtx (TImode);
   else
     dst = adjust_operand (dst, &start);
@@ -554,7 +554,7 @@ spu_expand_insv (rtx ops[])
     default:
       abort ();
     }
-  if (GET_CODE (ops[0]) == MEM)
+  if (MEM_P (ops[0]))
     {
       rtx low = gen_reg_rtx (SImode);
       rtx rotl = gen_reg_rtx (SImode);
@@ -2687,8 +2687,8 @@ uses_ls_unit(rtx_insn *insn)
 {
   rtx set = single_set (insn);
   if (set != 0
-      && (GET_CODE (SET_DEST (set)) == MEM
-	  || GET_CODE (SET_SRC (set)) == MEM))
+      && (MEM_P (SET_DEST (set))
+	  || MEM_P (SET_SRC (set))))
     return 1;
   return 0;
 }
diff --git a/gcc/config/spu/spu.md b/gcc/config/spu/spu.md
index 47705c65067..58459210cfd 100644
--- a/gcc/config/spu/spu.md
+++ b/gcc/config/spu/spu.md
@@ -4831,7 +4831,7 @@ selb\t%0,%4,%0,%3"
   emit_move_insn (offset, array_to_constant (V8HImode, arr));
   emit_move_insn (splatqi, array_to_constant (TImode, arr2));
 
-  gcc_assert (GET_CODE (operands[1]) == MEM);
+  gcc_assert (MEM_P (operands[1]));
   addr = force_reg (Pmode, XEXP (operands[1], 0));
   emit_insn (gen_andsi3 (addr_bits, addr, GEN_INT (0xF))); 
   emit_insn (gen_shufb (addr_bits_vec, addr_bits, addr_bits, splatqi));
diff --git a/gcc/config/stormy16/predicates.md b/gcc/config/stormy16/predicates.md
index 9f9edcb4b1b..3398efe91d8 100644
--- a/gcc/config/stormy16/predicates.md
+++ b/gcc/config/stormy16/predicates.md
@@ -65,10 +65,10 @@
 {
   if (GET_MODE (op) != mode)
     return 0;
-  if (GET_CODE (op) == MEM)
+  if (MEM_P (op))
     op = XEXP (op, 0);
   else if (SUBREG_P (op)
-	   && GET_CODE (XEXP (op, 0)) == MEM
+	   && MEM_P (XEXP (op, 0))
 	   && !MEM_VOLATILE_P (XEXP (op, 0)))
     op = XEXP (XEXP (op, 0), 0);
   else
@@ -95,7 +95,7 @@
 (define_predicate "xstormy16_splittable_below100_or_register"
   (match_code "mem,reg,subreg")
 {
-  if (GET_CODE (op) == MEM && MEM_VOLATILE_P (op))
+  if (MEM_P (op) && MEM_VOLATILE_P (op))
     return 0;
   return (xstormy16_below100_operand (op, mode)
 	  || register_operand (op, mode));
diff --git a/gcc/config/v850/predicates.md b/gcc/config/v850/predicates.md
index a1821a3bc29..f6cbdaabcaf 100644
--- a/gcc/config/v850/predicates.md
+++ b/gcc/config/v850/predicates.md
@@ -196,7 +196,7 @@
       dest = SET_DEST (vector_element);
       src = SET_SRC (vector_element);
 
-      if (GET_CODE (dest) != MEM
+      if (!MEM_P (dest)
 	  || GET_MODE (dest) != SImode
 	  || !REG_P (src)
 	  || GET_MODE (src) != SImode
@@ -286,7 +286,7 @@
       if (!REG_P (dest)
 	  || GET_MODE (dest) != SImode
 	  || ! register_is_ok_for_epilogue (dest, SImode)
-	  || GET_CODE (src) != MEM
+	  || !MEM_P (src)
 	  || GET_MODE (src) != SImode)
 	return 0;
 
@@ -358,7 +358,7 @@
       if (   !REG_P (dest)
 	  || GET_MODE (dest) != SImode
 	  || ! register_is_ok_for_epilogue (dest, SImode)
-	  || GET_CODE (src) != MEM
+	  || !MEM_P (src)
 	  || GET_MODE (src) != SImode)
 	return 0;
 
@@ -419,7 +419,7 @@
       dest = SET_DEST (vector_element);
       src  = SET_SRC (vector_element);
 
-      if (   GET_CODE (dest) != MEM
+      if (   !MEM_P (dest)
 	  || GET_MODE (dest) != SImode
 	  || !REG_P (src)
 	  || GET_MODE (src) != SImode
diff --git a/gcc/config/v850/v850.c b/gcc/config/v850/v850.c
index 3412e69563b..001b1baa8ec 100644
--- a/gcc/config/v850/v850.c
+++ b/gcc/config/v850/v850.c
@@ -583,7 +583,7 @@ v850_print_operand (FILE * file, rtx x, int code)
     case 'S':
       {
         /* If it's a reference to a TDA variable, use sst/sld vs. st/ld.  */
-        if (GET_CODE (x) == MEM && ep_memory_operand (x, GET_MODE (x), FALSE))
+        if (MEM_P (x) && ep_memory_operand (x, GET_MODE (x), FALSE))
           fputs ("s", file);
 
         break;
@@ -591,7 +591,7 @@ v850_print_operand (FILE * file, rtx x, int code)
     case 'T':
       {
 	/* Like an 'S' operand above, but for unsigned loads only.  */
-        if (GET_CODE (x) == MEM && ep_memory_operand (x, GET_MODE (x), TRUE))
+        if (MEM_P (x) && ep_memory_operand (x, GET_MODE (x), TRUE))
           fputs ("s", file);
 
         break;
@@ -866,7 +866,7 @@ output_move_single (rtx * operands)
 	    return "movhi hi(%F1),%.,%0\n\tmovea lo(%F1),%0,%0";
 	}
 
-      else if (GET_CODE (src) == MEM)
+      else if (MEM_P (src))
 	return "%S1ld%W1 %1,%0";
 
       else if (special_symbolref_operand (src, VOIDmode))
@@ -893,7 +893,7 @@ output_move_single (rtx * operands)
 	}
     }
 
-  else if (GET_CODE (dst) == MEM)
+  else if (MEM_P (dst))
     {
       if (REG_P (src))
 	return "%S0st%W0 %1,%0";
@@ -1066,7 +1066,7 @@ ep_memory_operand (rtx op, machine_mode mode, int unsigned_load)
   if (!TARGET_EP)
     return FALSE;
 
-  if (GET_CODE (op) != MEM)
+  if (!MEM_P (op))
     return FALSE;
 
   max_offset = ep_memory_offset (mode, unsigned_load);
@@ -1153,22 +1153,22 @@ Saved %d bytes (%d uses of register %s) in function %s, starting as insn %d, end
 	      /* Memory operands are signed by default.  */
 	      int unsignedp = FALSE;
 
-	      if (GET_CODE (SET_DEST (pattern)) == MEM
-		  && GET_CODE (SET_SRC (pattern)) == MEM)
+	      if (MEM_P (SET_DEST (pattern))
+		  && MEM_P (SET_SRC (pattern)))
 		p_mem = (rtx *)0;
 
-	      else if (GET_CODE (SET_DEST (pattern)) == MEM)
+	      else if (MEM_P (SET_DEST (pattern)))
 		p_mem = &SET_DEST (pattern);
 
-	      else if (GET_CODE (SET_SRC (pattern)) == MEM)
+	      else if (MEM_P (SET_SRC (pattern)))
 		p_mem = &SET_SRC (pattern);
 
 	      else if (GET_CODE (SET_SRC (pattern)) == SIGN_EXTEND
-		       && GET_CODE (XEXP (SET_SRC (pattern), 0)) == MEM)
+		       && MEM_P (XEXP (SET_SRC (pattern), 0)))
 		p_mem = &XEXP (SET_SRC (pattern), 0);
 
 	      else if (GET_CODE (SET_SRC (pattern)) == ZERO_EXTEND
-		       && GET_CODE (XEXP (SET_SRC (pattern), 0)) == MEM)
+		       && MEM_P (XEXP (SET_SRC (pattern), 0)))
 		{
 		  p_mem = &XEXP (SET_SRC (pattern), 0);
 		  unsignedp = TRUE;
@@ -1301,29 +1301,29 @@ v850_reorg (void)
 	      /* We might have (SUBREG (MEM)) here, so just get rid of the
 		 subregs to make this code simpler.  */
 	      if (SUBREG_P (dest)
-		  && (GET_CODE (SUBREG_REG (dest)) == MEM
+		  && (MEM_P (SUBREG_REG (dest))
 		      || REG_P (SUBREG_REG (dest))))
 		alter_subreg (&dest, false);
 	      if (SUBREG_P (src)
-		  && (GET_CODE (SUBREG_REG (src)) == MEM
+		  && (MEM_P (SUBREG_REG (src))
 		      || REG_P (SUBREG_REG (src))))
 		alter_subreg (&src, false);
 
-	      if (GET_CODE (dest) == MEM && GET_CODE (src) == MEM)
+	      if (MEM_P (dest) && MEM_P (src))
 		mem = NULL_RTX;
 
-	      else if (GET_CODE (dest) == MEM)
+	      else if (MEM_P (dest))
 		mem = dest;
 
-	      else if (GET_CODE (src) == MEM)
+	      else if (MEM_P (src))
 		mem = src;
 
 	      else if (GET_CODE (src) == SIGN_EXTEND
-		       && GET_CODE (XEXP (src, 0)) == MEM)
+		       && MEM_P (XEXP (src, 0)))
 		mem = XEXP (src, 0);
 
 	      else if (GET_CODE (src) == ZERO_EXTEND
-		       && GET_CODE (XEXP (src, 0)) == MEM)
+		       && MEM_P (XEXP (src, 0)))
 		{
 		  mem = XEXP (src, 0);
 		  unsignedp = TRUE;
diff --git a/gcc/config/visium/visium.c b/gcc/config/visium/visium.c
index 1621f4a6403..694456b5069 100644
--- a/gcc/config/visium/visium.c
+++ b/gcc/config/visium/visium.c
@@ -919,7 +919,7 @@ void
 prepare_move_operands (rtx *operands, machine_mode mode)
 {
   /* If the output is not a register, the input must be.  */
-  if (GET_CODE (operands[0]) == MEM && !reg_or_0_operand (operands[1], mode))
+  if (MEM_P (operands[0]) && !reg_or_0_operand (operands[1], mode))
     operands[1] = force_reg (mode, operands[1]);
 }
 
@@ -1046,7 +1046,7 @@ gr5_hazard_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
 
   /* Should be no stall/hazard if OUT_INSN is MEM := ???.  This only
      occurs prior to reload. */
-  if (GET_CODE (dest) == MEM)
+  if (MEM_P (dest))
     return 0;
 
   if (GET_CODE (dest) == STRICT_LOW_PART)
@@ -1058,7 +1058,7 @@ gr5_hazard_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
   in_set = single_set_and_flags (in_insn);
 
   /* If IN_INSN is MEM := MEM, it's the source that counts. */
-  if (GET_CODE (SET_SRC (in_set)) == MEM)
+  if (MEM_P (SET_SRC (in_set)))
     memexpr = XEXP (SET_SRC (in_set), 0);
   else
     memexpr = XEXP (SET_DEST (in_set), 0);
@@ -1150,7 +1150,7 @@ gr5_avoid_hazard (rtx_insn *insn, unsigned int *last_reg, bool *last_insn_call)
       const bool double_p = GET_MODE_SIZE (GET_MODE (dest)) > UNITS_PER_WORD;
       rtx memrtx = NULL;
 
-      if (GET_CODE (SET_SRC (set)) == MEM)
+      if (MEM_P (SET_SRC (set)))
 	{
 	  memrtx = XEXP (SET_SRC (set), 0);
 	  if (GET_CODE (dest) == STRICT_LOW_PART)
@@ -1183,7 +1183,7 @@ gr5_avoid_hazard (rtx_insn *insn, unsigned int *last_reg, bool *last_insn_call)
 	    }
 	}
 
-      else if (GET_CODE (dest) == MEM)
+      else if (MEM_P (dest))
 	memrtx = XEXP (dest, 0);
 
       else if (GET_MODE_CLASS (GET_MODE (dest)) != MODE_CC)
@@ -2120,7 +2120,7 @@ visium_split_double_move (rtx *operands, machine_mode mode)
     swap = true;
 
   /* Check memory to register where the base reg overlaps the destination.  */
-  if (REG_P (operands[0]) && GET_CODE (operands[1]) == MEM)
+  if (REG_P (operands[0]) && MEM_P (operands[1]))
     {
       rtx op = XEXP (operands[1], 0);
 
diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c
index 505b86397b9..85b4777a91d 100644
--- a/gcc/config/xtensa/xtensa.c
+++ b/gcc/config/xtensa/xtensa.c
@@ -525,7 +525,7 @@ xtensa_valid_move (machine_mode mode, rtx *operands)
 int
 smalloffset_mem_p (rtx op)
 {
-  if (GET_CODE (op) == MEM)
+  if (MEM_P (op))
     {
       rtx addr = XEXP (op, 0);
       if (REG_P (addr))
@@ -582,7 +582,7 @@ constantpool_mem_p (rtx op)
 {
   if (SUBREG_P (op))
     op = SUBREG_REG (op);
-  if (GET_CODE (op) == MEM)
+  if (MEM_P (op))
     return constantpool_address_p (XEXP (op, 0));
   return FALSE;
 }
@@ -2376,7 +2376,7 @@ print_operand (FILE *file, rtx x, int letter)
       break;
 
     case 'v':
-      if (GET_CODE (x) == MEM)
+      if (MEM_P (x))
 	{
 	  /* For a volatile memory reference, emit a MEMW before the
 	     load or store.  */
@@ -2388,7 +2388,7 @@ print_operand (FILE *file, rtx x, int letter)
       break;
 
     case 'N':
-      if (GET_CODE (x) == MEM
+      if (MEM_P (x)
 	  && (GET_MODE (x) == DFmode || GET_MODE (x) == DImode))
 	{
 	  x = adjust_address (x, GET_MODE (x) == DFmode ? E_SFmode : E_SImode,
@@ -2503,7 +2503,7 @@ print_operand (FILE *file, rtx x, int letter)
     default:
       if (REG_P (x) || SUBREG_P (x))
 	fprintf (file, "%s", reg_names[xt_true_regnum (x)]);
-      else if (GET_CODE (x) == MEM)
+      else if (MEM_P (x))
 	output_address (GET_MODE (x), XEXP (x, 0));
       else if (CONST_INT_P (x))
 	fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
diff --git a/gcc/dbxout.c b/gcc/dbxout.c
index 1d487a5475e..24672f62635 100644
--- a/gcc/dbxout.c
+++ b/gcc/dbxout.c
@@ -3329,11 +3329,11 @@ dbxout_common_check (tree decl, int *value)
     return NULL;
 
   home = DECL_RTL (decl);
-  if (home == NULL_RTX || GET_CODE (home) != MEM)
+  if (home == NULL_RTX || !MEM_P (home))
     return NULL;
 
   sym_addr = dbxout_expand_expr (DECL_VALUE_EXPR (decl));
-  if (sym_addr == NULL_RTX || GET_CODE (sym_addr) != MEM)
+  if (sym_addr == NULL_RTX || !MEM_P (sym_addr))
     return NULL;
 
   sym_addr = XEXP (sym_addr, 0);
diff --git a/gcc/df-scan.c b/gcc/df-scan.c
index 57d6efd709f..c3d52be4e49 100644
--- a/gcc/df-scan.c
+++ b/gcc/df-scan.c
@@ -2930,7 +2930,7 @@ df_uses_record (class df_collection_rec *collection_rec,
 				DF_REF_REG_USE, bb, insn_info, flags);
 		df_uses_record (collection_rec, &XEXP (dst, 2),
 				DF_REF_REG_USE, bb, insn_info, flags);
-                if (GET_CODE (XEXP (dst,0)) == MEM)
+                if (MEM_P (XEXP (dst,0)))
                   df_uses_record (collection_rec, &XEXP (dst, 0),
                                   DF_REF_REG_USE, bb, insn_info,
                                   flags);
diff --git a/gcc/fwprop.c b/gcc/fwprop.c
index 4d5b72e70e1..0b16dd2a9af 100644
--- a/gcc/fwprop.c
+++ b/gcc/fwprop.c
@@ -1146,7 +1146,7 @@ free_load_extend (rtx src, rtx_insn *insn)
       rtx patt = PATTERN (DF_REF_INSN (def));
 
       if (GET_CODE (patt) == SET
-	  && GET_CODE (SET_SRC (patt)) == MEM
+	  && MEM_P (SET_SRC (patt))
 	  && rtx_equal_p (SET_DEST (patt), reg))
 	return true;
     }
diff --git a/gcc/ifcvt.c b/gcc/ifcvt.c
index b93b692cb43..8ccf523c859 100644
--- a/gcc/ifcvt.c
+++ b/gcc/ifcvt.c
@@ -310,7 +310,7 @@ rtx_interchangeable_p (const_rtx a, const_rtx b)
   if (!rtx_equal_p (a, b))
     return false;
 
-  if (GET_CODE (a) != MEM)
+  if (!MEM_P (a))
     return true;
 
   /* A dead type-unsafe memory reference is legal, but a live type-unsafe memory
diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c
index 02f37535b0d..d1cb817df44 100644
--- a/gcc/simplify-rtx.c
+++ b/gcc/simplify-rtx.c
@@ -1242,7 +1242,7 @@ simplify_unary_operation_1 (enum rtx_code code, machine_mode mode, rtx op)
 
       /* A truncate of a memory is just loading the low part of the memory
 	 if we are not changing the meaning of the address. */
-      if (GET_CODE (op) == MEM
+      if (MEM_P (op)
 	  && !VECTOR_MODE_P (mode)
 	  && !MEM_VOLATILE_P (op)
 	  && !mode_dependent_address_p (XEXP (op, 0), MEM_ADDR_SPACE (op)))
diff --git a/gcc/var-tracking.c b/gcc/var-tracking.c
index 1d425d1acd9..e0ee278e044 100644
--- a/gcc/var-tracking.c
+++ b/gcc/var-tracking.c
@@ -2250,7 +2250,7 @@ vt_canonicalize_addr (dataflow_set *set, rtx oloc)
 static inline bool
 vt_canon_true_dep (dataflow_set *set, rtx mloc, rtx maddr, rtx loc)
 {
-  if (GET_CODE (loc) != MEM)
+  if (!MEM_P (loc))
     return false;
 
   rtx addr = vt_canonicalize_addr (set, XEXP (loc, 0));
@@ -2350,7 +2350,7 @@ clobber_overlapping_mems (dataflow_set *set, rtx loc)
 {
   struct overlapping_mems coms;
 
-  gcc_checking_assert (GET_CODE (loc) == MEM);
+  gcc_checking_assert (MEM_P (loc));
 
   coms.set = set;
   coms.loc = canon_rtx (loc);
@@ -2479,7 +2479,7 @@ val_bind (dataflow_set *set, rtx val, rtx loc, bool modified)
 	 dynamic tables.  ??? We should test this before emitting the
 	 micro-op in the first place.  */
       while (l)
-	if (GET_CODE (l->loc) == MEM && XEXP (l->loc, 0) == XEXP (loc, 0))
+	if (MEM_P (l->loc) && XEXP (l->loc, 0) == XEXP (loc, 0))
 	  break;
 	else
 	  l = l->next;
@@ -2612,7 +2612,7 @@ val_reset (dataflow_set *set, decl_or_value dv)
 	  else if (REG_P (node->loc))
 	    var_reg_decl_set (set, node->loc, node->init, cdv, 0,
 			      node->set_src, NO_INSERT);
-	  else if (GET_CODE (node->loc) == MEM)
+	  else if (MEM_P (node->loc))
 	    var_mem_decl_set (set, node->loc, node->init, cdv, 0,
 			      node->set_src, NO_INSERT);
 	  else
@@ -4735,7 +4735,7 @@ dataflow_set_preserve_mem_locs (variable **slot, dataflow_set *set)
 	  for (loc = var->var_part[0].loc_chain; loc; loc = loc->next)
 	    {
 	      /* We want to remove dying MEMs that don't refer to DECL.  */
-	      if (GET_CODE (loc->loc) == MEM
+	      if (MEM_P (loc->loc)
 		  && (MEM_EXPR (loc->loc) != decl
 		      || int_mem_offset (loc->loc) != 0)
 		  && mem_dies_at_call (loc->loc))
@@ -4779,7 +4779,7 @@ dataflow_set_preserve_mem_locs (variable **slot, dataflow_set *set)
 		}
 	    }
 
-	  if (GET_CODE (loc->loc) != MEM
+	  if (!MEM_P (loc->loc)
 	      || (MEM_EXPR (loc->loc) == decl
 		  && int_mem_offset (loc->loc) == 0)
 	      || !mem_dies_at_call (loc->loc))
@@ -4839,7 +4839,7 @@ dataflow_set_remove_mem_locs (variable **slot, dataflow_set *set)
       if (shared_var_p (var, set->vars))
 	{
 	  for (loc = var->var_part[0].loc_chain; loc; loc = loc->next)
-	    if (GET_CODE (loc->loc) == MEM
+	    if (MEM_P (loc->loc)
 		&& mem_dies_at_call (loc->loc))
 	      break;
 
@@ -4859,7 +4859,7 @@ dataflow_set_remove_mem_locs (variable **slot, dataflow_set *set)
       for (locp = &var->var_part[0].loc_chain, loc = *locp;
 	   loc; loc = *locp)
 	{
-	  if (GET_CODE (loc->loc) != MEM
+	  if (!MEM_P (loc->loc)
 	      || !mem_dies_at_call (loc->loc))
 	    {
 	      locp = &loc->next;
@@ -6835,7 +6835,7 @@ compute_bb_dataflow (basic_block bb)
 		  if (REG_P (uloc))
 		    var_reg_set (out, uloc, VAR_INIT_STATUS_UNINITIALIZED,
 				 NULL);
-		  else if (GET_CODE (uloc) == MEM)
+		  else if (MEM_P (uloc))
 		    var_mem_set (out, uloc, VAR_INIT_STATUS_UNINITIALIZED,
 				 NULL);
 		}
@@ -6943,7 +6943,7 @@ compute_bb_dataflow (basic_block bb)
 		var_regno_delete (out, REGNO (uloc));
 	      else if (MEM_P (uloc))
 		{
-		  gcc_checking_assert (GET_CODE (vloc) == MEM);
+		  gcc_checking_assert (MEM_P (vloc));
 		  gcc_checking_assert (dstv == vloc);
 		  if (dstv != vloc)
 		    clobber_overlapping_mems (out, vloc);
@@ -8726,7 +8726,7 @@ emit_note_insn_var_location (variable **varp, emit_note_data *data)
 	    continue;
 	  offset = VAR_PART_OFFSET (var, i);
 	  loc2 = var->var_part[i].cur_loc;
-	  if (loc2 && GET_CODE (loc2) == MEM
+	  if (loc2 && MEM_P (loc2)
 	      && GET_CODE (XEXP (loc2, 0)) == VALUE)
 	    {
 	      rtx depval = XEXP (loc2, 0);
@@ -8998,7 +8998,7 @@ notify_dependents_of_changed_value (rtx val, variable_table_type *htab,
 		{
 		  rtx loc = ivar->var_part[i].cur_loc;
 
-		  if (loc && GET_CODE (loc) == MEM
+		  if (loc && MEM_P (loc)
 		      && XEXP (loc, 0) == val)
 		    {
 		      variable_was_changed (ivar, NULL);
@@ -9333,7 +9333,7 @@ emit_notes_in_bb (basic_block bb, dataflow_set *set)
 		  if (REG_P (uloc))
 		    var_reg_set (set, uloc, VAR_INIT_STATUS_UNINITIALIZED,
 				 NULL);
-		  else if (GET_CODE (uloc) == MEM)
+		  else if (MEM_P (uloc))
 		    var_mem_set (set, uloc, VAR_INIT_STATUS_UNINITIALIZED,
 				 NULL);
 		}
@@ -9437,7 +9437,7 @@ emit_notes_in_bb (basic_block bb, dataflow_set *set)
 		var_regno_delete (set, REGNO (uloc));
 	      else if (MEM_P (uloc))
 		{
-		  gcc_checking_assert (GET_CODE (vloc) == MEM);
+		  gcc_checking_assert (MEM_P (vloc));
 		  gcc_checking_assert (vloc == dstv);
 		  if (vloc != dstv)
 		    clobber_overlapping_mems (set, vloc);
-- 
2.21.0


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