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Re: [PATCH, AArch64 v2 05/11] aarch64: Emit LSE st<op> instructions
- From: Richard Henderson <rth at twiddle dot net>
- To: James Greenhalgh <james dot greenhalgh at arm dot com>, Richard Henderson <richard dot henderson at linaro dot org>
- Cc: "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>, Ramana Radhakrishnan <Ramana dot Radhakrishnan at arm dot com>, "agraf at suse dot de" <agraf at suse dot de>, Marcus Shawcroft <Marcus dot Shawcroft at arm dot com>, Richard Earnshaw <Richard dot Earnshaw at arm dot com>, nd at arm dot com, will dot deacon at arm dot com
- Date: Wed, 31 Oct 2018 10:09:42 +0000
- Subject: Re: [PATCH, AArch64 v2 05/11] aarch64: Emit LSE st<op> instructions
- References: <20181002161915.18843-1-richard.henderson@linaro.org> <20181002161915.18843-6-richard.henderson@linaro.org> <20181030203228.GC22348@arm.com>
On 10/30/18 8:32 PM, James Greenhalgh wrote:
> On Tue, Oct 02, 2018 at 11:19:09AM -0500, Richard Henderson wrote:
>> When the result of an operation is not used, we can ignore the
>> result by storing to XZR. For two of the memory models, using
>> XZR with LD<op> has a preferred assembler alias, ST<op>.
>
> ST<op> has different semantics to LD<op>, in particular, ST<op> is not
> ordered by a DMB LD; so this could weaken the LDADD and break C11 semantics.
>
> The relevant Arm Arm text is:
>
> If the destination register is not one of WZR or XZR, LDADDA and
> LDADDAL load from memory with acquire semantics
You're quite right. I must have glossed over that clause when looking at this
before. I'll make sure there's a temp register to clobber for v2.
r~