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Re: [PATCH, AArch64 10/11] aarch64: Implement TImode compare-and-swap
- From: Richard Henderson <richard dot henderson at linaro dot org>
- To: Matthew Malcomson <matthew dot malcomson at arm dot com>, rth7680 at gmail dot com, gcc-patches at gcc dot gnu dot org
- Cc: ramana dot radhakrishnan at arm dot com, agraf at suse dot de, matz at suse dot de
- Date: Thu, 27 Sep 2018 09:32:15 -0700
- Subject: Re: [PATCH, AArch64 10/11] aarch64: Implement TImode compare-and-swap
- References: <20180926050355.32746-1-richard.henderson@linaro.org> <20180926050355.32746-11-richard.henderson@linaro.org> <3460dd10-4d9a-1def-3f9b-5f7a1afe5906@arm.com>
On 9/27/18 6:04 AM, Matthew Malcomson wrote:
> Hi Richard,
>
>
> On 26/09/18 06:03, rth7680@gmail.com wrote:
>> From: Richard Henderson <richard.henderson@linaro.org>
>>
>> This pattern will only be used with the __sync functions, because
>> we do not yet have a bare TImode atomic load.
>>
>>
> I don't have any comment on the overall aim of the patch series, but in
> this particular
> patch it looks like you doesn't ensure the register pairs for casp are
> even-odd.
>
> This is the restriction in the Arm Arm decode for casp variants as
> if Rs<0> == '1' then UnallocatedEncoding();
> if Rt<0> == '1' then UnallocatedEncoding();
Oops. I missed this bit when reading the docs. Thanks.
I'll incorporate your even register class patch into the next round.
r~