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Re: [GCC][PATCH v2][Aarch64] Exploiting BFXIL when OR-ing two AND-operations with appropriate bitmasks
- From: Christophe Lyon <christophe dot lyon at linaro dot org>
- To: Kyrill Tkachov <kyrylo dot tkachov at foss dot arm dot com>
- Cc: sam dot tebbs at arm dot com, James Greenhalgh <James dot Greenhalgh at arm dot com>, gcc Patches <gcc-patches at gcc dot gnu dot org>, Marcus Shawcroft <Marcus dot Shawcroft at arm dot com>, Richard Earnshaw <Richard dot Earnshaw at arm dot com>, nd <nd at arm dot com>
- Date: Thu, 20 Sep 2018 18:36:52 +0200
- Subject: Re: [GCC][PATCH v2][Aarch64] Exploiting BFXIL when OR-ing two AND-operations with appropriate bitmasks
- References: <44d5392a-f033-ed0d-d679-116b3eafa0b9@arm.com> <20180828225320.GE22590@arm.com> <b2d1a56d-e0db-91e1-4fdc-044a3fdb9a9e@arm.com> <20180911152000.GA37978@arm.com> <4ab58a71-c586-410c-9fc2-5e9bb0c07de6@arm.com> <5B9A329D.4060009@foss.arm.com> <CAKdteOYh2bGYz_YStvAj0nB_YRXnLGarucK_k=BC-LkbJAzqDw@mail.gmail.com> <5BA21766.9040507@foss.arm.com>
On Wed, 19 Sep 2018 at 11:31, Kyrill Tkachov
<kyrylo.tkachov@foss.arm.com> wrote:
>
> Hi Christophe,
>
> On 18/09/18 23:00, Christophe Lyon wrote:
> > On Thu, 13 Sep 2018 at 11:49, Kyrill Tkachov
> > <kyrylo.tkachov@foss.arm.com> wrote:
> >>
> >> On 13/09/18 10:25, Sam Tebbs wrote:
> >>> On 09/11/2018 04:20 PM, James Greenhalgh wrote:
> >>>> On Tue, Sep 04, 2018 at 10:13:43AM -0500, Sam Tebbs wrote:
> >>>>> Hi James,
> >>>>>
> >>>>> Thanks for the feedback. Here is an update with the changes you proposed
> >>>>> and an updated changelog.
> >>>>>
> >>>>> gcc/
> >>>>> 2018-09-04 Sam Tebbs <sam.tebbs@arm.com>
> >>>>>
> >>>>> PR target/85628
> >>>>> * config/aarch64/aarch64.md (*aarch64_bfxil):
> >>>>> Define.
> >>>>> * config/aarch64/constraints.md (Ulc): Define
> >>>>> * config/aarch64/aarch64-protos.h (aarch64_high_bits_all_ones_p):
> >>>>> Define.
> >>>>> * config/aarch64/aarch64.c (aarch64_high_bits_all_ones_p): New function.
> >>>>>
> >>>>> gcc/testsuite
> >>>>> 2018-09-04 Sam Tebbs <sam.tebbs@arm.com>
> >>>>>
> >>>>> PR target/85628
> >>>>> * gcc.target/aarch64/combine_bfxil.c: New file.
> >>>>> * gcc.target/aarch64/combine_bfxil_2.c: New file.
> >>>>>
> >>>>>
> >>>> <snip>
> >>>>
> >>>>> +/* Return true if I's bits are consecutive ones from the MSB. */
> >>>>> +bool
> >>>>> +aarch64_high_bits_all_ones_p (HOST_WIDE_INT i)
> >>>>> +{
> >>>>> + return exact_log2(-i) != HOST_WIDE_INT_M1;
> >>>>> +}
> >>>> You need a space in here between the function name and the bracket:
> >>>>
> >>>> exact_log2 (-i)
> >>>>
> >>>>
> >>>>> +extern void abort(void);
> >>>> The same comment applies multiple places in this file.
> >>>>
> >>>> Likewise; if (
> >>>>
> >>>> Otherwise, OK, please apply with those fixes.
> >>>>
> >>>> Thanks,
> >>>> James
> >>> Thanks for noticing that, here's the fixed version.
> >>>
> >> Thanks Sam, I've committed the patch on your behalf with r264264.
> >> If you want to get write-after-approval access to the SVN repo to commit patches yourself in the future
> >> please fill out the form at https://sourceware.org/cgi-bin/pdw/ps_form.cgi putting my address from the MAINTAINERS file as the approver.
> >>
> > Hi,
> >
> > You've probably already noticed by now since you fixed the
> > combine_bfi_1 issue introduced by this commit, but it add another
> > regression:
> > FAIL: gcc.target/aarch64/copysign-bsl.c scan-assembler b(sl|it|if)\tv[0-9]
>
> Yeah, that one is a bit more involved as it's an unexpected interaction with the copysign BSL pattern.
> Would you be able to file a bugzilla issue to track it?
>
Sure, this is: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87369
> Thanks,
> Kyrill
>
> > Christophe
> >
> >> Kyrill
> >>
> >>> Sam
>