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Re: [GCC][PATCH][Aarch64] Make common aarch64 options target-dependent
- From: "Richard Earnshaw (lists)" <Richard dot Earnshaw at arm dot com>
- To: Sam Tebbs <sam dot tebbs at arm dot com>, "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>
- Cc: Marcus Shawcroft <marcus dot shawcroft at arm dot com>, James Greenhalgh <james dot greenhalgh at arm dot com>, nd <nd at arm dot com>
- Date: Thu, 16 Aug 2018 10:46:43 +0100
- Subject: Re: [GCC][PATCH][Aarch64] Make common aarch64 options target-dependent
- References: <a9a5872a-a02a-f9a1-5c27-c5ad393d5ce0@arm.com>
On 16/08/18 09:45, Sam Tebbs wrote:
> Hi all,
>
> This patch replaces the "Common" attribute in some aarch64 options with
> "Target"
> to make them target-dependent. This doesn't affect their behaviour or
> how they
> are documented with "--help", but does mean that they follow the option
> specification that target-specific options are given the "Target"
> attribute.
>
> Tested by ensuring the changed options are still accepted as before and
> that
> they aren't invokable from an invalid target. Bootstrapped and
> regression tested
> on aarch64-none-elf with ... regressions.
>
> Is this ok for trunk? If so could someone commit it on my behalf? I
> don't have
> commit rights.
>
> gcc/
> 2018-08-16 Sam Tebbs<sam.tebbs@arm.com>
Two spaces between your name and email address.
>
> * config/aarch64/aarch64.opt (mlow-precision-recip-sqrt,
> mlow-precision-sqrt, mlow-precision-div, mverbose-cost-dump):
> Replace
If you split a function list across a line break, end each line with a
close parenthesis and start the next with an open-parenthesis. So:
* config/aarch64/aarch64.opt (mlow-precision-recip-sqrt)
(mlow-precision-sqrt, mlow-precision-div, mverbose-cost-dump):
> "Common" with "Target".
>
I've fixed this up and applied.
R.
PS, if you can use hard tabs for indenting your ChangeLog text it will
make my life a lot easier, as I don't have to fix it up manually.
>
> latest.patch
>
>
> diff --git a/gcc/config/aarch64/aarch64.opt b/gcc/config/aarch64/aarch64.opt
> index bc9b22a4464c1e82b9183410c088e6757721e79b..c8e820422245496eaf09dd6546472e1ff9e90d4f 100644
> --- a/gcc/config/aarch64/aarch64.opt
> +++ b/gcc/config/aarch64/aarch64.opt
> @@ -167,20 +167,20 @@ EnumValue
> Enum(aarch64_ra_sign_scope_t) String(all) Value(AARCH64_FUNCTION_ALL)
>
> mlow-precision-recip-sqrt
> -Common Var(flag_mrecip_low_precision_sqrt) Optimization
> +Target Var(flag_mrecip_low_precision_sqrt) Optimization
> Enable the reciprocal square root approximation. Enabling this reduces
> precision of reciprocal square root results to about 16 bits for
> single precision and to 32 bits for double precision.
>
> mlow-precision-sqrt
> -Common Var(flag_mlow_precision_sqrt) Optimization
> +Target Var(flag_mlow_precision_sqrt) Optimization
> Enable the square root approximation. Enabling this reduces
> precision of square root results to about 16 bits for
> single precision and to 32 bits for double precision.
> If enabled, it implies -mlow-precision-recip-sqrt.
>
> mlow-precision-div
> -Common Var(flag_mlow_precision_div) Optimization
> +Target Var(flag_mlow_precision_div) Optimization
> Enable the division approximation. Enabling this reduces
> precision of division results to about 16 bits for
> single precision and to 32 bits for double precision.
> @@ -212,7 +212,7 @@ Target RejectNegative Joined Enum(sve_vector_bits) Var(aarch64_sve_vector_bits)
> -msve-vector-bits=N Set the number of bits in an SVE vector register to N.
>
> mverbose-cost-dump
> -Common Undocumented Var(flag_aarch64_verbose_cost)
> +Target Undocumented Var(flag_aarch64_verbose_cost)
> Enables verbose cost model dumping in the debug dump files.
>
> mtrack-speculation
>