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Re: [PATCH] [AArch64, Falkor] Adjust Falkor's sign extend reg+reg address cost
- From: James Greenhalgh <james dot greenhalgh at arm dot com>
- To: Luis Machado <luis dot machado at linaro dot org>
- Cc: "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>, Richard Earnshaw <Richard dot Earnshaw at arm dot com>, <nd at arm dot com>
- Date: Tue, 31 Jul 2018 23:54:51 +0100
- Subject: Re: [PATCH] [AArch64, Falkor] Adjust Falkor's sign extend reg+reg address cost
- References: <1532543723-26647-1-git-send-email-luis.machado@linaro.org>
On Wed, Jul 25, 2018 at 01:35:23PM -0500, Luis Machado wrote:
> Adjust Falkor's register_sextend cost from 4 to 3. This fixes a testsuite
> failure in gcc.target/aarch64/extend.c:ldr_sxtw where GCC was generating
> a sbfiz instruction rather than a load with sign extension.
>
> No performance changes.
OK if this is what is best for your subtarget.
Thanks,
James
>
> gcc/ChangeLog:
>
> 2018-07-25 Luis Machado <luis.machado@linaro.org>
>
> * config/aarch64/aarch64.c (qdf24xx_addrcost_table)
> <register_sextend>: Set to 3.