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Re: [PATCH, aarch64 3/4] aarch64: Add movprfx alternatives for predicate patterns


On 07/02/2018 04:55 AM, Richard Sandiford wrote:
>> +;; Predicated floating-point operations with select matching output.
>> +(define_insn "*cond_<optab><mode>_0"
>> +  [(set (match_operand:SVE_F 0 "register_operand" "+w, w, ?&w")
>>  	(unspec:SVE_F
>> -	  [(match_operand:<VPRED> 1 "register_operand" "Upl")
>> +	  [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl")
>>  	   (unspec:SVE_F
>> -	     [(match_operand:SVE_F 2 "register_operand" "0")
>> -	      (match_operand:SVE_F 3 "register_operand" "w")]
>> +	     [(match_dup 1)
>> +	      (match_operand:SVE_F 2 "register_operand" "0, w, w")
>> +	      (match_operand:SVE_F 3 "register_operand" "w, 0, w")]
>> +	     SVE_COND_FP_BINARY)
>> +	   (match_dup 0)]
>> +	  UNSPEC_SEL))]
>> +  "TARGET_SVE"
>> +  "@
>> +   <sve_fp_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
>> +   <sve_fp_op_rev>\t%0.<Vetype>, %1/m, %0.<Vetype>, %2.<Vetype>
>> +   movprfx\t%0, %1/m, %2\;<sve_fp_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>"
>> +  [(set_attr "movprfx" "*,*,yes")]
>> +)
> 
> Reintroduces a (match_dup 1) into the SVE_COND_FP_BINARY.
> 
> OK otherwise, thanks.

Feh, and fixed again in patch 4.
I've squashed all 4 patches for final commit,
so the intermediate breakage is gone.

Thanks for the review.


r~


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