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[AArch64][PATCH 0/2] PR target/83009: Relax strict address checking for store pair lanes
- From: Andre Simoes Dias Vieira <Andre dot SimoesDiasVieira at arm dot com>
- To: "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>
- Cc: nd <nd at arm dot com>
- Date: Thu, 7 Jun 2018 17:00:31 +0000
- Subject: [AArch64][PATCH 0/2] PR target/83009: Relax strict address checking for store pair lanes
- Nodisclaimer: True
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Hi,
This patch series is aimed at resolving PR83009 that identified a missing optimization opportunity for Store pair lanes. The second patch of these series was initially reverted because it lead to a wrong codegen. This codegen was a latent issue that was now being hit due to STP's being generated in more cases. The first patch in this series remedies that latent issue.
Andre Vieira (2):
Fix addressing printing of LDP/STP
PR target/83009: Relax strict address checking for store pair lanes