Re: [PATCH] rtlanal: Fix nonzero_bits for non-load paradoxical subregs (PR85925)

[Richard Sandiford <rdsandiford at googlemail dot com>]

Eric Botcazou <ebotcazou@adacore.com> writes:
>> In the PR we have insns:
>> 
>> Trying 23 -> 24:
>>    23: r123:SI=zero_extend(r122:HI)
>>       REG_DEAD r122:HI
>>    24: [r115:SI]=r123:SI
>>       REG_DEAD r123:SI
>> 
>> which should be combined to
>> 
>> (set (mem:SI (reg/f:SI 115 [ pretmp_19 ]) [1 *pretmp_19+0 S4 A32])
>>     (and:SI (subreg:SI (reg:HI 122) 0)
>>         (const_int 32767 [0x7fff])))
>> 
>> But nonzero_bits of reg:HI 122 is 0x7fff, and nonzero_bits1 thinks it
>> then also has that same nonzero_bits for the subreg.  This is not
>> correct: the bit outside of HImode are undefined.  load_extend_op
>> applies to loads from memory only, not anything else.  Which means the
>> whole AND is optimised away.
>
> No, this is done on purpose for WORD_REGISTER_OPERATIONS targets and your 
> patch will pessimize them.  I'm going to have a look at the PR then.

I can see why WORD_REGISTER_OPERATIONS allows some REG cases,
but why does LOAD_EXTEND_OP have an effect on them?  The doc says:

@defmac WORD_REGISTER_OPERATIONS
Define this macro to 1 if operations between registers with integral mode
smaller than a word are always performed on the entire register.  To be
more explicit, if you start with a pair of @code{word_mode} registers with
known values and you do a subword, for example @code{QImode}, addition on
the low part of the registers, then the compiler may consider that the
result has a known value in @code{word_mode} too if the macro is defined
to 1.  Most RISC machines have this property and most CISC machines do not.
@end defmac

which doesn't make it sound like LOAD_EXTEND_OP has a direct effect
on the (cached) lhs of an arithmetic operation.

Ah well.  I guess I'm just glad that AArch64 doesn't define this :-)

Richard