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Re: [PATCH] rtlanal: Fix nonzero_bits for non-load paradoxical subregs (PR85925)


> In the PR we have insns:
> 
> Trying 23 -> 24:
>    23: r123:SI=zero_extend(r122:HI)
>       REG_DEAD r122:HI
>    24: [r115:SI]=r123:SI
>       REG_DEAD r123:SI
> 
> which should be combined to
> 
> (set (mem:SI (reg/f:SI 115 [ pretmp_19 ]) [1 *pretmp_19+0 S4 A32])
>     (and:SI (subreg:SI (reg:HI 122) 0)
>         (const_int 32767 [0x7fff])))
> 
> But nonzero_bits of reg:HI 122 is 0x7fff, and nonzero_bits1 thinks it
> then also has that same nonzero_bits for the subreg.  This is not
> correct: the bit outside of HImode are undefined.  load_extend_op
> applies to loads from memory only, not anything else.  Which means the
> whole AND is optimised away.

No, this is done on purpose for WORD_REGISTER_OPERATIONS targets and your 
patch will pessimize them.  I'm going to have a look at the PR then.

-- 
Eric Botcazou


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