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[PATCH] GFNI and misc other fixes (PR target/83604)
- From: Jakub Jelinek <jakub at redhat dot com>
- To: Uros Bizjak <ubizjak at gmail dot com>, Kirill Yukhin <kirill dot yukhin at gmail dot com>
- Cc: gcc-patches at gcc dot gnu dot org, Julia Koval <julia dot koval at intel dot com>, Sebastian Peryt <sebastian dot peryt at intel dot com>
- Date: Thu, 28 Dec 2017 11:07:17 +0100
- Subject: [PATCH] GFNI and misc other fixes (PR target/83604)
- Authentication-results: sourceware.org; auth=none
- Reply-to: Jakub Jelinek <jakub at redhat dot com>
Hi!
Martin reported sse-13.c ICEs without all the options it has in dg-options.
The problem is that the GFNI builtins used incorrect ISA masks and the
headers too. GFNI has one SSE encoded instruction (but that really needs
SSE2 rather than SSE, because it uses V16QImode which is not enabled just
for SSE), 2 AVX VEC encoded ones (without masking) and then EVEX encoded
ones with masking where for *_mask we sometimes also need AVX512BW in
addition to GFNI + {AVX512VL,AVX512F} in the CPUID column in the pdf.
Of course, such combinations don't really work properly with the current
handling of the builtin masks, so I've finally analyzed all cases where we
combine multiple ISA options in masks and found out that these days
what actually is an exception is where we require one isa or another isa,
rather than both or all 3. So instead of adding further and further
exceptions, this patch changes the general rule, by default we require
all the listed ISAs to be enabled and have 3 exceptions to that rule
(SSE | 3DNOW_A), (FMA | FMA4) and (SSE4_2 | CRC32), where we are looking for
at least one of those enabled rather than both (but, if these are ored with
other ISA masks, we require one of the two from the pair and all others).
Another thing is that 3 intrinsic headers were missing the boilerplate,
some were using incorrect macros etc.
The new testcase unfortunately still has to require -msse2 -mmmx, because
some intrin headers aren't fully correct in their pragmas (don't enable
MMX where required etc.).
Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
2017-12-28 Jakub Jelinek <jakub@redhat.com>
PR target/83604
* config/i386/i386-builtin.def
(__builtin_ia32_vgf2p8affineinvqb_v64qi,
__builtin_ia32_vgf2p8affineqb_v64qi, __builtin_ia32_vgf2p8mulb_v64qi):
Require also OPTION_MASK_ISA_AVX512F in addition to
OPTION_MASK_ISA_GFNI.
(__builtin_ia32_vgf2p8affineinvqb_v16qi_mask,
__builtin_ia32_vgf2p8affineqb_v16qi_mask): Require
OPTION_MASK_ISA_AVX512VL instead of OPTION_MASK_ISA_SSE in addition
to OPTION_MASK_ISA_GFNI.
(__builtin_ia32_vgf2p8mulb_v32qi_mask): Require
OPTION_MASK_ISA_AVX512VL in addition to OPTION_MASK_ISA_GFNI and
OPTION_MASK_ISA_AVX512BW.
(__builtin_ia32_vgf2p8mulb_v16qi_mask): Require
OPTION_MASK_ISA_AVX512VL instead of OPTION_MASK_ISA_AVX512BW in
addition to OPTION_MASK_ISA_GFNI.
(__builtin_ia32_vgf2p8affineinvqb_v16qi,
__builtin_ia32_vgf2p8affineqb_v16qi, __builtin_ia32_vgf2p8mulb_v16qi):
Require OPTION_MASK_ISA_SSE2 instead of OPTION_MASK_ISA_SSE in addition
to OPTION_MASK_ISA_GFNI.
* config/i386/i386.c (def_builtin): Change to builtin isa/isa2 being
a requirement for all ISAs rather than any of them with a few
exceptions.
(ix86_add_new_builtins): Clear OPTION_MASK_ISA_64BIT from isa before
processing.
(ix86_expand_builtin): Require all ISAs from builtin's isa and isa2
bitmasks to be enabled with 3 exceptions, instead of requiring any
enabled ISA with lots of exceptions.
* config/i386/sse.md (vgf2p8affineinvqb_<mode><mask_name>,
vgf2p8affineqb_<mode><mask_name>, vgf2p8mulb_<mode><mask_name>):
Change avx512bw in isa attribute to avx512f.
* config/i386/sgxintrin.h: Add license boilerplate.
* config/i386/vaesintrin.h: Likewise. Fix macro spelling __AVX512F
to __AVX512F__ and __AVX512VL to __AVX512VL__.
(_mm256_aesdec_epi128, _mm256_aesdeclast_epi128, _mm256_aesenc_epi128,
_mm256_aesenclast_epi128): Enable temporarily avx if __AVX__ is not
defined.
* config/i386/gfniintrin.h (_mm_gf2p8mul_epi8,
_mm_gf2p8affineinv_epi64_epi8, _mm_gf2p8affine_epi64_epi8): Enable
temporarily sse2 rather than sse if not enabled already.
* gcc.target/i386/sse-26.c: New test.
--- gcc/config/i386/i386-builtin.def.jj 2017-12-25 12:58:49.860181619 +0100
+++ gcc/config/i386/i386-builtin.def 2017-12-28 10:18:41.997233122 +0100
@@ -2530,24 +2530,24 @@ BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPT
BDESC (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpshldv_v2di_maskz, "__builtin_ia32_vpshldv_v2di_maskz", IX86_BUILTIN_VPSHLDVV2DI_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT)
/* GFNI */
-BDESC (OPTION_MASK_ISA_GFNI, CODE_FOR_vgf2p8affineinvqb_v64qi, "__builtin_ia32_vgf2p8affineinvqb_v64qi", IX86_BUILTIN_VGF2P8AFFINEINVQB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_INT)
+BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512F, CODE_FOR_vgf2p8affineinvqb_v64qi, "__builtin_ia32_vgf2p8affineinvqb_v64qi", IX86_BUILTIN_VGF2P8AFFINEINVQB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_INT)
BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8affineinvqb_v64qi_mask, "__builtin_ia32_vgf2p8affineinvqb_v64qi_mask", IX86_BUILTIN_VGF2P8AFFINEINVQB512MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_INT_V64QI_UDI)
BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX, CODE_FOR_vgf2p8affineinvqb_v32qi, "__builtin_ia32_vgf2p8affineinvqb_v32qi", IX86_BUILTIN_VGF2P8AFFINEINVQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT)
-BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vgf2p8affineinvqb_v32qi_mask, "__builtin_ia32_vgf2p8affineinvqb_v32qi_mask", IX86_BUILTIN_VGF2P8AFFINEINVQB256MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT_V32QI_USI)
-BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_SSE, CODE_FOR_vgf2p8affineinvqb_v16qi, "__builtin_ia32_vgf2p8affineinvqb_v16qi", IX86_BUILTIN_VGF2P8AFFINEINVQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT)
-BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_SSE, CODE_FOR_vgf2p8affineinvqb_v16qi_mask, "__builtin_ia32_vgf2p8affineinvqb_v16qi_mask", IX86_BUILTIN_VGF2P8AFFINEINVQB128MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT_V16QI_UHI)
-BDESC (OPTION_MASK_ISA_GFNI, CODE_FOR_vgf2p8affineqb_v64qi, "__builtin_ia32_vgf2p8affineqb_v64qi", IX86_BUILTIN_VGF2P8AFFINEQB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_INT)
+BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8affineinvqb_v32qi_mask, "__builtin_ia32_vgf2p8affineinvqb_v32qi_mask", IX86_BUILTIN_VGF2P8AFFINEINVQB256MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT_V32QI_USI)
+BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_SSE2, CODE_FOR_vgf2p8affineinvqb_v16qi, "__builtin_ia32_vgf2p8affineinvqb_v16qi", IX86_BUILTIN_VGF2P8AFFINEINVQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT)
+BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vgf2p8affineinvqb_v16qi_mask, "__builtin_ia32_vgf2p8affineinvqb_v16qi_mask", IX86_BUILTIN_VGF2P8AFFINEINVQB128MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT_V16QI_UHI)
+BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512F, CODE_FOR_vgf2p8affineqb_v64qi, "__builtin_ia32_vgf2p8affineqb_v64qi", IX86_BUILTIN_VGF2P8AFFINEQB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_INT)
BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8affineqb_v64qi_mask, "__builtin_ia32_vgf2p8affineqb_v64qi_mask", IX86_BUILTIN_VGF2P8AFFINEQB512MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_INT_V64QI_UDI)
BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX, CODE_FOR_vgf2p8affineqb_v32qi, "__builtin_ia32_vgf2p8affineqb_v32qi", IX86_BUILTIN_VGF2P8AFFINEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT)
-BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vgf2p8affineqb_v32qi_mask, "__builtin_ia32_vgf2p8affineqb_v32qi_mask", IX86_BUILTIN_VGF2P8AFFINEQB256MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT_V32QI_USI)
-BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_SSE, CODE_FOR_vgf2p8affineqb_v16qi, "__builtin_ia32_vgf2p8affineqb_v16qi", IX86_BUILTIN_VGF2P8AFFINEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT)
-BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_SSE, CODE_FOR_vgf2p8affineqb_v16qi_mask, "__builtin_ia32_vgf2p8affineqb_v16qi_mask", IX86_BUILTIN_VGF2P8AFFINEQB128MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT_V16QI_UHI)
-BDESC (OPTION_MASK_ISA_GFNI, CODE_FOR_vgf2p8mulb_v64qi, "__builtin_ia32_vgf2p8mulb_v64qi", IX86_BUILTIN_VGF2P8MULB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI)
+BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8affineqb_v32qi_mask, "__builtin_ia32_vgf2p8affineqb_v32qi_mask", IX86_BUILTIN_VGF2P8AFFINEQB256MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT_V32QI_USI)
+BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_SSE2, CODE_FOR_vgf2p8affineqb_v16qi, "__builtin_ia32_vgf2p8affineqb_v16qi", IX86_BUILTIN_VGF2P8AFFINEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT)
+BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vgf2p8affineqb_v16qi_mask, "__builtin_ia32_vgf2p8affineqb_v16qi_mask", IX86_BUILTIN_VGF2P8AFFINEQB128MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT_V16QI_UHI)
+BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512F, CODE_FOR_vgf2p8mulb_v64qi, "__builtin_ia32_vgf2p8mulb_v64qi", IX86_BUILTIN_VGF2P8MULB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI)
BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8mulb_v64qi_mask, "__builtin_ia32_vgf2p8mulb_v64qi_mask", IX86_BUILTIN_VGF2P8MULB512MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI)
BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX, CODE_FOR_vgf2p8mulb_v32qi, "__builtin_ia32_vgf2p8mulb_v32qi", IX86_BUILTIN_VGF2P8MULB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI)
-BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8mulb_v32qi_mask, "__builtin_ia32_vgf2p8mulb_v32qi_mask", IX86_BUILTIN_VGF2P8MULB256MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI)
-BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_SSE, CODE_FOR_vgf2p8mulb_v16qi, "__builtin_ia32_vgf2p8mulb_v16qi", IX86_BUILTIN_VGF2P8MULB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI)
-BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8mulb_v16qi_mask, "__builtin_ia32_vgf2p8mulb_v16qi_mask", IX86_BUILTIN_VGF2P8MULB128MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI)
+BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8mulb_v32qi_mask, "__builtin_ia32_vgf2p8mulb_v32qi_mask", IX86_BUILTIN_VGF2P8MULB256MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI)
+BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_SSE2, CODE_FOR_vgf2p8mulb_v16qi, "__builtin_ia32_vgf2p8mulb_v16qi", IX86_BUILTIN_VGF2P8MULB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI)
+BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vgf2p8mulb_v16qi_mask, "__builtin_ia32_vgf2p8mulb_v16qi_mask", IX86_BUILTIN_VGF2P8MULB128MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI)
/* VNNI */
--- gcc/config/i386/i386.c.jj 2017-12-25 12:58:49.743183059 +0100
+++ gcc/config/i386/i386.c 2017-12-27 21:48:04.952256742 +0100
@@ -29798,28 +29798,20 @@ def_builtin (HOST_WIDE_INT mask, const c
{
ix86_builtins_isa[(int) code].isa = mask;
- /* OPTION_MASK_ISA_AVX512{F,VL,BW} have special meaning. Despite of
- generic case, where any bit set means that built-in is enable, this
- bit must be *and-ed* with another one. E.g.:
- OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL
- means that *both* cpuid bits must be set for the built-in to
- be available. Handle this here. */
+ mask &= ~OPTION_MASK_ISA_64BIT;
+
+ /* Filter out the masks most often ored together with others. */
if ((mask & ix86_isa_flags & OPTION_MASK_ISA_AVX512VL)
&& mask != OPTION_MASK_ISA_AVX512VL)
mask &= ~OPTION_MASK_ISA_AVX512VL;
if ((mask & ix86_isa_flags & OPTION_MASK_ISA_AVX512BW)
&& mask != OPTION_MASK_ISA_AVX512BW)
mask &= ~OPTION_MASK_ISA_AVX512BW;
- if ((mask & ix86_isa_flags & OPTION_MASK_ISA_AVX512F)
- && mask != OPTION_MASK_ISA_AVX512F)
- mask &= ~OPTION_MASK_ISA_AVX512F;
- mask &= ~OPTION_MASK_ISA_64BIT;
if (mask == 0
|| (mask & ix86_isa_flags) != 0
|| (lang_hooks.builtin_function
== lang_hooks.builtin_function_ext_scope))
-
{
tree type = ix86_get_builtin_func_type (tcode);
decl = add_builtin_function (name, type, code, BUILT_IN_MD,
@@ -29954,6 +29946,8 @@ def_builtin_pure2 (HOST_WIDE_INT mask, c
static void
ix86_add_new_builtins (HOST_WIDE_INT isa, HOST_WIDE_INT isa2)
{
+ isa &= ~OPTION_MASK_ISA_64BIT;
+
if ((isa & deferred_isa_values) == 0
&& (isa2 & deferred_isa_values2) == 0)
return;
@@ -35371,41 +35365,34 @@ ix86_expand_builtin (tree exp, rtx targe
}
}
- /* Determine whether the builtin function is available under the current ISA.
- Originally the builtin was not created if it wasn't applicable to the
- current ISA based on the command line switches. With function specific
- options, we need to check in the context of the function making the call
- whether it is supported. Treat AVX512{VL,BW,F} and MMX specially. For
- other flags, if isa includes more than one ISA bit, treat those are
- requiring any of them. For AVX512VL, require both AVX512VL and the
- non-AVX512VL ISAs. Likewise for MMX, require both MMX and the non-MMX
- ISAs. Similarly for AVX512F and AVX512BW.
- Similarly for 64BIT, but we shouldn't be building such builtins
- at all, -m64 is a whole TU option. */
- if (((ix86_builtins_isa[fcode].isa
- & ~(OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_MMX
- | OPTION_MASK_ISA_64BIT | OPTION_MASK_ISA_AVX512BW
- | OPTION_MASK_ISA_AVX512F))
- && !(ix86_builtins_isa[fcode].isa
- & ~(OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_MMX
- | OPTION_MASK_ISA_64BIT | OPTION_MASK_ISA_AVX512BW
- | OPTION_MASK_ISA_AVX512F)
- & ix86_isa_flags))
- || ((ix86_builtins_isa[fcode].isa & OPTION_MASK_ISA_AVX512VL)
- && !(ix86_isa_flags & OPTION_MASK_ISA_AVX512VL))
- || ((ix86_builtins_isa[fcode].isa & OPTION_MASK_ISA_AVX512BW)
- && !(ix86_isa_flags & OPTION_MASK_ISA_AVX512BW))
- || ((ix86_builtins_isa[fcode].isa & OPTION_MASK_ISA_AVX512F)
- && !(ix86_isa_flags & OPTION_MASK_ISA_AVX512F))
- || ((ix86_builtins_isa[fcode].isa & OPTION_MASK_ISA_MMX)
- && !(ix86_isa_flags & OPTION_MASK_ISA_MMX))
- || (ix86_builtins_isa[fcode].isa2
- && !(ix86_builtins_isa[fcode].isa2 & ix86_isa_flags2)))
- {
- char *opts = ix86_target_string (ix86_builtins_isa[fcode].isa,
- ix86_builtins_isa[fcode].isa2, 0, 0,
- NULL, NULL, (enum fpmath_unit) 0,
- false);
+ HOST_WIDE_INT isa = ix86_isa_flags;
+ HOST_WIDE_INT isa2 = ix86_isa_flags2;
+ HOST_WIDE_INT bisa = ix86_builtins_isa[fcode].isa;
+ HOST_WIDE_INT bisa2 = ix86_builtins_isa[fcode].isa2;
+ /* The general case is we require all the ISAs specified in bisa{,2}
+ to be enabled.
+ The exceptions are:
+ OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A
+ OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32
+ OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4
+ where for each this pair it is sufficient if either of the ISAs is
+ enabled, plus if it is ored with other options also those others. */
+ if (((bisa & (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A))
+ == (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A))
+ && (isa & (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A)) != 0)
+ isa |= (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A);
+ if (((bisa & (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32))
+ == (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32))
+ && (isa & (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32)) != 0)
+ isa |= (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32);
+ if (((bisa & (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4))
+ == (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4))
+ && (isa & (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4)) != 0)
+ isa |= (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4);
+ if ((bisa & isa) != bisa || (bisa2 & isa2) != bisa2)
+ {
+ char *opts = ix86_target_string (bisa, bisa2, 0, 0, NULL, NULL,
+ (enum fpmath_unit) 0, false);
if (!opts)
error ("%qE needs unknown isa option", fndecl);
else
--- gcc/config/i386/sse.md.jj 2017-12-27 18:43:32.200347561 +0100
+++ gcc/config/i386/sse.md 2017-12-27 19:50:01.421655504 +0100
@@ -20092,7 +20092,7 @@ (define_insn "vgf2p8affineinvqb_<mode><m
gf2p8affineinvqb\t{%3, %2, %0| %0, %2, %3}
vgf2p8affineinvqb\t{%3, %2, %1, %0<mask_operand4>| %0<mask_operand4>, %1, %2, %3}
vgf2p8affineinvqb\t{%3, %2, %1, %0<mask_operand4>| %0<mask_operand4>, %1, %2, %3}"
- [(set_attr "isa" "noavx,avx,avx512bw")
+ [(set_attr "isa" "noavx,avx,avx512f")
(set_attr "prefix_data16" "1,*,*")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,maybe_evex,evex")
@@ -20110,7 +20110,7 @@ (define_insn "vgf2p8affineqb_<mode><mask
gf2p8affineqb\t{%3, %2, %0| %0, %2, %3}
vgf2p8affineqb\t{%3, %2, %1, %0<mask_operand4>| %0<mask_operand4>, %1, %2, %3}
vgf2p8affineqb\t{%3, %2, %1, %0<mask_operand4>| %0<mask_operand4>, %1, %2, %3}"
- [(set_attr "isa" "noavx,avx,avx512bw")
+ [(set_attr "isa" "noavx,avx,avx512f")
(set_attr "prefix_data16" "1,*,*")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,maybe_evex,evex")
@@ -20127,7 +20127,7 @@ (define_insn "vgf2p8mulb_<mode><mask_nam
gf2p8mulb\t{%2, %0| %0, %2}
vgf2p8mulb\t{%2, %1, %0<mask_operand3>| %0<mask_operand3>, %1, %2}
vgf2p8mulb\t{%2, %1, %0<mask_operand3>| %0<mask_operand3>, %1, %2}"
- [(set_attr "isa" "noavx,avx,avx512bw")
+ [(set_attr "isa" "noavx,avx,avx512f")
(set_attr "prefix_data16" "1,*,*")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,maybe_evex,evex")
--- gcc/config/i386/sgxintrin.h.jj 2017-01-12 22:29:01.667841856 +0100
+++ gcc/config/i386/sgxintrin.h 2017-12-27 21:51:10.161351355 +0100
@@ -1,3 +1,26 @@
+/* Copyright (C) 2017 Free Software Foundation, Inc.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GCC is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
#ifndef _SGXINTRIN_H_INCLUDED
#define _SGXINTRIN_H_INCLUDED
--- gcc/config/i386/vaesintrin.h.jj 2017-12-15 11:47:28.818673904 +0100
+++ gcc/config/i386/vaesintrin.h 2017-12-27 21:57:08.772534536 +0100
@@ -1,9 +1,32 @@
+/* Copyright (C) 2017 Free Software Foundation, Inc.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GCC is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
#ifndef __VAESINTRIN_H_INCLUDED
#define __VAESINTRIN_H_INCLUDED
-#ifndef __VAES__
+#if !defined(__VAES__) || !defined(__AVX__)
#pragma GCC push_options
-#pragma GCC target("vaes")
+#pragma GCC target("vaes,avx")
#define __DISABLE_VAES__
#endif /* __VAES__ */
@@ -43,7 +66,7 @@ _mm256_aesenclast_epi128 (__m256i __A, _
#endif /* __DISABLE_VAES__ */
-#if !defined(__VAES__) || !defined(__AVX512F)
+#if !defined(__VAES__) || !defined(__AVX512F__)
#pragma GCC push_options
#pragma GCC target("vaes,avx512f")
#define __DISABLE_VAESF__
@@ -85,7 +108,7 @@ _mm512_aesenclast_epi128 (__m512i __A, _
#pragma GCC pop_options
#endif /* __DISABLE_VAES__ */
-#if !defined(__VAES__) || !defined(__AVX512VL)
+#if !defined(__VAES__) || !defined(__AVX512VL__)
#pragma GCC push_options
#pragma GCC target("vaes,avx512vl")
#define __DISABLE_VAESVL__
--- gcc/config/i386/gfniintrin.h.jj 2017-11-16 10:33:30.575529350 +0100
+++ gcc/config/i386/gfniintrin.h 2017-12-28 10:19:20.098247577 +0100
@@ -28,9 +28,9 @@
#ifndef _GFNIINTRIN_H_INCLUDED
#define _GFNIINTRIN_H_INCLUDED
-#if !defined(__GFNI__) || !defined(__SSE__)
+#if !defined(__GFNI__) || !defined(__SSE2__)
#pragma GCC push_options
-#pragma GCC target("gfni,sse")
+#pragma GCC target("gfni,sse2")
#define __DISABLE_GFNI__
#endif /* __GFNI__ */
--- gcc/testsuite/gcc.target/i386/sse-26.c.jj 2017-12-27 22:05:20.525779512 +0100
+++ gcc/testsuite/gcc.target/i386/sse-26.c 2017-12-28 10:37:56.084692062 +0100
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse2 -mmmx -mno-sse3 -mno-3dnow -mno-fma -mno-fxsr -mno-xsave -mno-rtm -mno-prfchw -mno-rdseed -mno-adx -mno-prefetchwt1 -mno-clflushopt -mno-xsavec -mno-xsaves -mno-clwb -mno-mwaitx -mno-clzero -mno-pku -mno-rdpid -mno-gfni -mno-ibt -mno-shstk -mno-vaes -mno-vpclmulqdq" } */
+/* { dg-add-options bind_pic_locally } */
+
+#include "sse-13.c"
Jakub