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Re: [PATCH 3/4] [SPARC] Errata workaround for GRLIB-TN-0010
- From: Eric Botcazou <ebotcazou at adacore dot com>
- To: Daniel Cederman <cederman at gaisler dot com>
- Cc: gcc-patches at gcc dot gnu dot org, sebastian dot huber at embedded-brains dot de, daniel at gaisler dot com
- Date: Fri, 24 Nov 2017 11:57:41 +0100
- Subject: Re: [PATCH 3/4] [SPARC] Errata workaround for GRLIB-TN-0010
- Authentication-results: sourceware.org; auth=none
- References: <20171120125003.22670-1-cederman@gaisler.com> <20171120125003.22670-4-cederman@gaisler.com>
> 2017-11-17 Daniel Cederman <cederman@gaisler.com>
>
> * config/sparc/sparc.c (atomic_insn_p): New function.
> (sparc_do_work_around_errata): Insert NOP instructions to
> prevent sequences that could trigger the TN-0010 errata for
> UT700.
> * config/sparc/sync.md (atomic_compare_and_swap_leon3_1): Make
> instruction referable in atomic_insns_p.
OK for mainline and 7 branch modulo the following nits:
> +/* True if complex atomic instruction. */
> +
> +static int
> +atomic_insn_p (rtx_insn *insn)
'bool' instead of 'int'. "True if INSN is an atomic instruction."
I'd rename the function into "atomic_insn_for_leon3_p" since you're handling
only the LEON3 instructions.
> @@ -1021,6 +1037,33 @@ sparc_do_work_around_errata (void
> emit_insn_before (gen_nop (), target);
> }
>
> + /* Insert a NOP between load instruction and atomic
> + instruction. Insert a NOP at branch target if load
> + in delay slot and atomic instruction at branch target. */
Double space after colon.
> + if (sparc_fix_ut700
> + && NONJUMP_INSN_P (insn)
> + && (set = single_set (insn)) != NULL_RTX
> + && MEM_P (SET_SRC (set))
> + && REG_P (SET_DEST (set)))
> + {
> + if (jump)
> + {
> + rtx_insn *target;
> +
> + target = next_active_insn (JUMP_LABEL_AS_INSN (jump));
rtx_insn *target
= next_active_insn (JUMP_LABEL_AS_INSN (jump));
> + if (target
> + && atomic_insn_p (target))
On a single line.
--
Eric Botcazou