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Re: [PATCH][AArch64] Restrict POST_INC operand in aarch64_simd_mem_operand_p to register
- From: Kyrill Tkachov <kyrylo dot tkachov at foss dot arm dot com>
- To: Dominik Inführ <dominik dot infuehr at theobroma-systems dot com>, GCC Patches <gcc-patches at gcc dot gnu dot org>
- Cc: "Richard Earnshaw (lists)" <richard dot earnshaw at arm dot com>, James Greenhalgh <james dot greenhalgh at arm dot com>, Marcus Shawcroft <marcus dot shawcroft at arm dot com>
- Date: Tue, 31 Oct 2017 14:10:23 +0000
- Subject: Re: [PATCH][AArch64] Restrict POST_INC operand in aarch64_simd_mem_operand_p to register
- Authentication-results: sourceware.org; auth=none
- References: <8D47A986-1D89-4AD6-8DD7-90563EA74C99@theobroma-systems.com>
[cc'ing aarch64 maintainers]
Hi Dominik,
On 31/10/17 13:47, Dominik Inführ wrote:
Hi,
I have a custom optimization pass, that moves an expression into an POST_INC-expression. GCC then ICE’s in df-scan.c since it expects REG_P to be true for POST_INC’s operand. aarch64_simd_mem_operand_p doesn’t seem to check POST_INC’s operand. Here is a patch that fixes this for me, although I am not sure if this is the right way to address this. GCC bootstraps and it causes no test regressions.
The documentation for POST_INC says that its operand has to be a MEM or
a REG.
Anything else is invalid RTL.
AArch64 only supports REGs as an operand to POST_INC.
The existing implementation of aarch64_simd_lane_bounds indeed doesn't
properly reject non-REG operands to
POST_INC, so I think your patch is correct, in that we should be tighter
to make sure we don't accept any MEMs.
But you'll need an approval from an aarch64 maintainer before committing.
However, I suggest you check your pass to make sure it doesn't try to
put any arbitrary RTL into a POST_INC, because
otherwise some other parts of the compiler might blow up.
Thanks,
Kyrill
Dominik
ChangeLog:
2017-10-31 Dominik Infuehr <dominik.infuehr@theobroma-systems.com>
* config/aarch64/aarch64.c (aarch64_simd_mem_operand_p): Check
if register given as operand for POST_INC.
-----
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index ed30b8c..bb61506 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -11850,8 +11850,15 @@ aarch64_simd_lane_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high,
bool
aarch64_simd_mem_operand_p (rtx op)
{
- return MEM_P (op) && (GET_CODE (XEXP (op, 0)) == POST_INC
- || REG_P (XEXP (op, 0)));
+ if (!MEM_P (op))
+ return false;
+
+ rtx opnd = XEXP (op, 0);
+
+ if (GET_CODE (opnd) == POST_INC)
+ opnd = XEXP(opnd, 0);
+
+ return REG_P (opnd);
}
/* Emit a register copy from operand to operand, taking care not to