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Re: [PATCH][aarch64] Fix target/pr77729 - missed optimization related to zero extension
- From: Segher Boessenkool <segher at kernel dot crashing dot org>
- To: Wilco Dijkstra <Wilco dot Dijkstra at arm dot com>
- Cc: "Ellcey, Steve" <Steve dot Ellcey at cavium dot com>, Kyrylo Tkachov <Kyrylo dot Tkachov at arm dot com>, nd <nd at arm dot com>, GCC Patches <gcc-patches at gcc dot gnu dot org>
- Date: Wed, 13 Sep 2017 19:30:26 -0500
- Subject: Re: [PATCH][aarch64] Fix target/pr77729 - missed optimization related to zero extension
- Authentication-results: sourceware.org; auth=none
- References: <HE1PR0801MB2058C7979FC494209CFDD6C4836E0@HE1PR0801MB2058.eurprd08.prod.outlook.com> <HE1PR0801MB20589C1EEA6CB1F50C47D9BF836E0@HE1PR0801MB2058.eurprd08.prod.outlook.com>
On Wed, Sep 13, 2017 at 10:41:33PM +0000, Wilco Dijkstra wrote:
> Steve Ellcey wrote:
>
> > And in aarch64 rtl expansion I see:
> >
> > (insn 10 9 11 (set (reg:QI 81)
> > (mem:QI (reg/v/f:DI 80 [ string ]) [0 *string_9(D)+0 S1 A8])) "pr77729.c":3 -1
> > (nil))
>
> Yes using QI/HI mode anywhere in the RTL seems perverse and incorrect given AArch64
> doesn't support registers narrower than 32 bits. Shift counts seem to have the same
> issue and expand into very complex sequences of ANDs with subreg - and nobody seems
> to understand what subreg really means...
Right, just use SImode for shift counts and life is so much brighter.
> My feeling is that we should only use SI/DI mode in patterns and aggressively widen all
> 8/16-bit operations to SI mode (which is what C requires anyway).
You don't need to do anything for this even, just don't define any
operations on smaller modes (other than mov and the extends, and the
few operations you perhaps actually do have).
Segher