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Re: [PATCH] [Aarch64] Optimize subtract in shift counts
- From: Wilco Dijkstra <Wilco dot Dijkstra at arm dot com>
- To: Richard Biener <richard dot guenther at gmail dot com>, "richard dot sandiford at linaro dot org" <richard dot sandiford at linaro dot org>
- Cc: "kenner at vlsi1 dot ultra dot nyu dot edu" <kenner at vlsi1 dot ultra dot nyu dot edu>, "Michael Collison" <Michael dot Collison at arm dot com>, GCC Patches <gcc-patches at gcc dot gnu dot org>, nd <nd at arm dot com>
- Date: Tue, 22 Aug 2017 10:30:52 +0000
- Subject: Re: [PATCH] [Aarch64] Optimize subtract in shift counts
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Hi,
The main reason we have this issue is that DImode can be treated as a
vector of size 1. As a result we do not know whether the shift is an integer
or SIMD instruction. One way around this is to never use the SIMD variant,
another is to introduce V1DImode for vectors of size 1.
Short term I believe the first option is best - I don't think scalar operations executed
as SIMD instructions are useful in general, and these shifts are likely never used in
reality, so we're adding a lot of complexity and potential bugs .
Long term we need to compute register classes and do instruction selection
much earlier so this doesn't increase complexity of register allocation and machine
descriptors.
Wilco