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[PATCH][GCC][AArch64] Fix pattern guard relaxations that are allowing more constants than they should.
- From: Tamar Christina <tamar dot christina at arm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Cc: nd at arm dot com, james dot greenhalgh at arm dot com, Richard dot Earnshaw at arm dot com, Marcus dot Shawcroft at arm dot com
- Date: Fri, 11 Aug 2017 12:01:40 +0100
- Subject: [PATCH][GCC][AArch64] Fix pattern guard relaxations that are allowing more constants than they should.
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Hi All,
Hi previous float immediate patches changed
aarch64_reg_or_fp_zero into aarch64_reg_or_fp_float
for each of the movdf/sf/hf causing the RTL to contain
stores to memory it would never be able to find a matching
pattern for. Reload would then decide to store them to a
register instead.
This didn't cause any incorrect code or failing tests but did change
scheduling does producing more inefficient code.
The predicate is not reverted.
Regression tested on aarch64-none-linux-gnu and no regressions.
OK for trunk?
Thanks,
Tamar
gcc/
2017-08-11 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64.md (mov<mode>): Change.
(*movhf_aarch64, *movsf_aarch64, *movdf_aarch64):
aarch64_reg_or_fp_float into aarch64_reg_or_fp_zero.
* config/aarch64/predicates.md (aarch64_reg_or_fp_float): Removed.
--
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 7609fdba22627f15ed7630c371587b14b72e02ec..ba9c4479605fc6e001822a0f0e1df7d61ab58e0f 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -1076,7 +1076,7 @@
[(set (match_operand:HF 0 "nonimmediate_operand" "=w,w ,?r,w,w ,w ,w,m,r,m ,r")
(match_operand:HF 1 "general_operand" "Y ,?rY, w,w,Ufc,Uvi,m,w,m,rY,r"))]
"TARGET_FLOAT && (register_operand (operands[0], HFmode)
- || aarch64_reg_or_fp_float (operands[1], HFmode))"
+ || aarch64_reg_or_fp_zero (operands[1], HFmode))"
"@
movi\\t%0.4h, #0
fmov\\t%h0, %w1
@@ -1099,7 +1099,7 @@
[(set (match_operand:SF 0 "nonimmediate_operand" "=w,w ,?r,w,w ,w ,w,m,r,m ,r,r")
(match_operand:SF 1 "general_operand" "Y ,?rY, w,w,Ufc,Uvi,m,w,m,rY,r,M"))]
"TARGET_FLOAT && (register_operand (operands[0], SFmode)
- || aarch64_reg_or_fp_float (operands[1], SFmode))"
+ || aarch64_reg_or_fp_zero (operands[1], SFmode))"
"@
movi\\t%0.2s, #0
fmov\\t%s0, %w1
@@ -1123,7 +1123,7 @@
[(set (match_operand:DF 0 "nonimmediate_operand" "=w, w ,?r,w,w ,w ,w,m,r,m ,r,r")
(match_operand:DF 1 "general_operand" "Y , ?rY, w,w,Ufc,Uvi,m,w,m,rY,r,N"))]
"TARGET_FLOAT && (register_operand (operands[0], DFmode)
- || aarch64_reg_or_fp_float (operands[1], DFmode))"
+ || aarch64_reg_or_fp_zero (operands[1], DFmode))"
"@
movi\\t%d0, #0
fmov\\t%d0, %x1
diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md
index 95d28cfa33c6e06c47b6c666af6d8c2d6cef20f4..11243c4ce00aa7d16a886bb24b01180801c68f4e 100644
--- a/gcc/config/aarch64/predicates.md
+++ b/gcc/config/aarch64/predicates.md
@@ -57,11 +57,6 @@
(ior (match_operand 0 "register_operand")
(match_test "op == const0_rtx"))))
-(define_predicate "aarch64_reg_or_fp_float"
- (ior (match_operand 0 "register_operand")
- (and (match_code "const_double")
- (match_test "aarch64_float_const_rtx_p (op)"))))
-
(define_predicate "aarch64_reg_or_fp_zero"
(ior (match_operand 0 "register_operand")
(and (match_code "const_double")