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Re: Patch ping : Aarch64/ARM
- From: James Greenhalgh <james dot greenhalgh at arm dot com>
- To: Jakub Jelinek <jakub at redhat dot com>
- Cc: Marcus Shawcroft <marcus dot shawcroft at arm dot com>, Richard Earnshaw <richard dot earnshaw at arm dot com>, Ramana Radhakrishnan <ramana dot radhakrishnan at arm dot com>, Nick Clifton <nickc at redhat dot com>, <gcc-patches at gcc dot gnu dot org>, <nd at arm dot com>
- Date: Tue, 1 Aug 2017 09:04:44 +0100
- Subject: Re: Patch ping : Aarch64/ARM
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On Tue, Aug 01, 2017 at 09:06:38AM +0200, Jakub Jelinek wrote:
> Hi!
>
> I'd like to ping the aarch64/arm parts of the
> http://gcc.gnu.org/ml/gcc-patches/2017-07/msg01511.html
> vec_init/vec_extract patch. The generic part of the patch
> has been approved by Richard, and the other config/*/ parts have
> either been approved by their respective maintainers, or I'm going
> to check in as obvious, ia64 simple enough obvious change, and
> powerpcspe and spu changes very similar to the rs6000 one that has
> been approved.
>
> So I just need an ack for the aarch64 and arm changes. Ok for trunk?
The AArch64 parts are OK.
Thanks,
James
---
> --- gcc/config/aarch64/aarch64-simd.md.jj2017-07-24 15:01:21.000000000 +0200
> +++ gcc/config/aarch64/aarch64-simd.md2017-07-24 17:19:05.660170375 +0200
> @@ -5617,9 +5617,9 @@ (define_expand "aarch64_set_qreg<VSTRUCT
> DONE;
> })
>
> -;; Standard pattern name vec_init<mode>.
> +;; Standard pattern name vec_init<mode><Vel>.
>
> -(define_expand "vec_init<mode>"
> +(define_expand "vec_init<mode><Vel>"
> [(match_operand:VALL_F16 0 "register_operand" "")
> (match_operand 1 "" "")]
> "TARGET_SIMD"
> @@ -5674,9 +5674,9 @@ (define_insn "aarch64_urecpe<mode>"
> "urecpe\\t%0.<Vtype>, %1.<Vtype>"
> [(set_attr "type" "neon_fp_recpe_<Vetype><q>")])
>
> -;; Standard pattern name vec_extract<mode>.
> +;; Standard pattern name vec_extract<mode><Vel>.
>
> -(define_expand "vec_extract<mode>"
> +(define_expand "vec_extract<mode><Vel>"
> [(match_operand:<VEL> 0 "aarch64_simd_nonimmediate_operand" "")
> (match_operand:VALL_F16 1 "register_operand" "")
> (match_operand:SI 2 "immediate_operand" "")]
> --- gcc/config/aarch64/iterators.md.jj2017-03-19 11:57:22.000000000 +0100
> +++ gcc/config/aarch64/iterators.md2017-07-24 17:17:50.318091273 +0200
> @@ -520,6 +520,17 @@ (define_mode_attr VEL [(V8QI "QI") (V16Q
> (SI "SI") (HI "HI")
> (QI "QI")])
>
> +;; Define element mode for each vector mode (lower case).
> +(define_mode_attr Vel [(V8QI "qi") (V16QI "qi")
> +(V4HI "hi") (V8HI "hi")
> +(V2SI "si") (V4SI "si")
> +(DI "di") (V2DI "di")
> +(V4HF "hf") (V8HF "hf")
> +(V2SF "sf") (V4SF "sf")
> +(V2DF "df") (DF "df")
> +(SI "si") (HI "hi")
> +(QI "qi")])
> +
> ;; 64-bit container modes the inner or scalar source mode.
> (define_mode_attr VCOND [(HI "V4HI") (SI "V2SI")
> (V4HI "V4HI") (V8HI "V4HI")