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[patch,avr,v6,applied] Backports of: PR81407, PR81305, PR79883 + PR67353.
- From: Georg-Johann Lay <avr at gjlay dot de>
- To: gcc-patches <gcc-patches at gcc dot gnu dot org>
- Cc: Denis Chertykov <chertykov at gmail dot com>
- Date: Thu, 27 Jul 2017 10:20:42 +0200
- Subject: [patch,avr,v6,applied] Backports of: PR81407, PR81305, PR79883 + PR67353.
- Authentication-results: sourceware.org; auth=none
Applied $subject to gcc-6-branch.
Johann
https://gcc.gnu.org/r250574
gcc/
Backport from 2017-07-12 trunk r250151.
PR target/81407
* config/avr/avr.c (avr_encode_section_info)
[progmem && !TREE_READONLY]: Error if progmem object needs
constructing.
https://gcc.gnu.org/r250576
gcc/
Backport from 2017-07-05 trunk r249995.
PR target/81305
* config/avr/avr.c (avr_out_movhi_mr_r_xmega) [CONSTANT_ADDRESS_P]:
Don't depend on "optimize > 0".
(out_movhi_r_mr, out_movqi_mr_r): Same.
(out_movhi_mr_r, out_movqi_r_mr): Same.
(avr_address_cost) [CONSTANT_ADDRESS_P]: Don't depend cost for
io_address_operand on "optimize > 0".
gcc/testsuite/
Backport from 2017-07-05 trunk r249995, r249996.
PR target/81305
* gcc.target/avr/isr-test.h: New file.
* gcc.target/avr/torture/isr-01-simple.c: New test.
* gcc.target/avr/torture/isr-02-call.c: New test.
* gcc.target/avr/torture/isr-03-fixed.c: New test.
https://gcc.gnu.org/r250577
gcc/
Backport from 2016-06-15 trunk r237486.
Backport from 2017-07-12 trunk r250156.
PR target/79883
PR target/67353
* config/avr/avr.c (avr_set_current_function): Warn misspelled ISR
only if -Wmisspelled-isr is on. In diagnostic messages: Quote
keywords and (parts of) identifiers.
[WITH_AVRLIBC]: Warn functions named "ISR", "SIGNAL" or "INTERUPT".
* doc/invoke.texi (AVR Options) <-Wmisspelled-isr>: Document.
Index: gcc/config/avr/avr.c
===================================================================
--- gcc/config/avr/avr.c (revision 250573)
+++ gcc/config/avr/avr.c (revision 250574)
@@ -9591,18 +9591,26 @@ avr_encode_section_info (tree decl, rtx
if (new_decl_p
&& decl && DECL_P (decl)
- && NULL_TREE == DECL_INITIAL (decl)
&& !DECL_EXTERNAL (decl)
&& avr_progmem_p (decl, DECL_ATTRIBUTES (decl)))
{
- // Don't warn for (implicit) aliases like in PR80462.
- tree asmname = DECL_ASSEMBLER_NAME (decl);
- varpool_node *node = varpool_node::get_for_asmname (asmname);
- bool alias_p = node && node->alias;
+ if (!TREE_READONLY (decl))
+ {
+ // This might happen with C++ if stuff needs constructing.
+ error ("variable %q+D with dynamic initialization put "
+ "into program memory area", decl);
+ }
+ else if (NULL_TREE == DECL_INITIAL (decl))
+ {
+ // Don't warn for (implicit) aliases like in PR80462.
+ tree asmname = DECL_ASSEMBLER_NAME (decl);
+ varpool_node *node = varpool_node::get_for_asmname (asmname);
+ bool alias_p = node && node->alias;
- if (!alias_p)
- warning (OPT_Wuninitialized, "uninitialized variable %q+D put into "
- "program memory area", decl);
+ if (!alias_p)
+ warning (OPT_Wuninitialized, "uninitialized variable %q+D put "
+ "into program memory area", decl);
+ }
}
default_encode_section_info (decl, rtl, new_decl_p);
Index: gcc/testsuite/gcc.target/avr/isr-test.h
===================================================================
--- gcc/testsuite/gcc.target/avr/isr-test.h (nonexistent)
+++ gcc/testsuite/gcc.target/avr/isr-test.h (revision 250576)
@@ -0,0 +1,282 @@
+#ifndef ISR_TEST_H
+#define ISR_TEST_H
+
+#include <string.h>
+
+#define ISR(N,...) \
+__attribute__ ((used, externally_visible , ## __VA_ARGS__)) \
+ void __vector_##N (void); \
+ void __vector_##N (void)
+
+#define SFR(ADDR) (*(unsigned char volatile*) (__AVR_SFR_OFFSET__ + (ADDR)))
+#define CORE_SFRS SFR (0x38)
+#define SREG SFR (0x3F)
+#define SPL SFR (0x3D)
+#define EIND SFR (0x3C)
+#define RAMPZ SFR (0x3B)
+#define RAMPY SFR (0x3A)
+#define RAMPX SFR (0x39)
+#define RAMPD SFR (0x38)
+
+#ifdef __AVR_HAVE_JMP_CALL__
+#define VEC_SIZE 4
+#else
+#define VEC_SIZE 2
+#endif
+
+#ifdef __AVR_TINY__
+#define FIRST_REG 16
+#else
+#define FIRST_REG 0
+#endif
+
+#define CR "\n\t"
+
+typedef struct
+{
+ unsigned char sfrs[8];
+ unsigned char gprs[32 - FIRST_REG];
+} regs_t;
+
+regs_t reginfo1, reginfo2;
+
+__attribute__((noinline))
+static void clear_reginfo (void)
+{
+ memset (reginfo1.sfrs, 0, sizeof (reginfo1.sfrs));
+ memset (reginfo2.sfrs, 0, sizeof (reginfo2.sfrs));
+}
+
+__attribute__((noinline))
+static void compare_reginfo (unsigned long gpr_ignore)
+{
+ signed char regno;
+ const unsigned char *preg1 = ®info1.gprs[0];
+ const unsigned char *preg2 = ®info2.gprs[0];
+
+ if (memcmp (®info1, ®info2, 8))
+ __builtin_abort();
+
+ gpr_ignore >>= FIRST_REG;
+
+ for (regno = FIRST_REG; regno < 32;
+ regno++, preg1++, preg2++, gpr_ignore >>= 1)
+ {
+ if (gpr_ignore & 1)
+ continue;
+
+ if (*preg1 != *preg2)
+ {
+ static signed char volatile failed_regno;
+ failed_regno = regno;
+ __builtin_abort();
+ }
+ }
+}
+
+/* STore GPR */
+#define ST(regno,M) \
+ CR "sts %[" #M "]+8-%[first]+" #regno ", r" #regno
+
+/* STore SFR */
+#define ST_SFR(sfr, n_sfr, M) \
+ CR "in __tmp_reg__,%i[s_" #sfr "]" \
+ CR "sts %[" #M "]+" #n_sfr ", __tmp_reg__"
+
+/* Named asm OPerand for SFR */
+#define OP_SFR(sfr) \
+ , [s_ ## sfr] "n" (&(sfr))
+
+/* Write funny value to SFR */
+#define XX_SFR(sfr) \
+ CR "dec r31 $ out %i[s_" #sfr "], r31"
+
+/* Write 0 to SFR */
+#define OO_SFR(sfr) \
+ CR "out %i[s_" #sfr "], __zero_reg__"
+
+/* Macros for SREG */
+#define ST_SREG(M) ST_SFR (SREG,0,M)
+#define OP_SREG OP_SFR (SREG)
+#define XX_SREG XX_SFR (SREG)
+
+/* Macros for EIND */
+#if defined __AVR_HAVE_EIJMP_EICALL__
+#define ST_EIND(M) ST_SFR (EIND,1,M)
+#define OP_EIND OP_SFR (EIND)
+#else
+#define ST_EIND(M) /* empty */
+#define OP_EIND /* empty */
+#endif
+
+/* Macros for RAMPX */
+#if defined (__AVR_HAVE_RAMPX__)
+#define ST_RAMPX(M) ST_SFR (RAMPX,2,M)
+#define OP_RAMPX OP_SFR (RAMPX)
+#define XX_RAMPX XX_SFR (RAMPX)
+#define OO_RAMPX OO_SFR (RAMPX)
+#else
+#define ST_RAMPX(M) /* empty */
+#define OP_RAMPX /* empty */
+#define XX_RAMPX /* empty */
+#define OO_RAMPX /* empty */
+#endif
+
+/* Macros for RAMPY */
+#if defined (__AVR_HAVE_RAMPY__)
+#define ST_RAMPY(M) ST_SFR (RAMPY,3,M)
+#define OP_RAMPY OP_SFR (RAMPY)
+#define XX_RAMPY XX_SFR (RAMPY)
+#define OO_RAMPY OO_SFR (RAMPY)
+#else
+#define ST_RAMPY(M) /* empty */
+#define OP_RAMPY /* empty */
+#define XX_RAMPY /* empty */
+#define OO_RAMPY /* empty */
+#endif
+
+/* Macros for RAMPZ */
+#if defined (__AVR_HAVE_RAMPZ__)
+#define ST_RAMPZ(M) ST_SFR (RAMPZ,4,M)
+#define OP_RAMPZ OP_SFR (RAMPZ)
+#define XX_RAMPZ XX_SFR (RAMPZ)
+#define OO_RAMPZ OO_SFR (RAMPZ)
+#else
+#define ST_RAMPZ(M) /* empty */
+#define OP_RAMPZ /* empty */
+#define XX_RAMPZ /* empty */
+#define OO_RAMPZ /* empty */
+#endif
+
+/* Macros for RAMPD */
+#if defined (__AVR_HAVE_RAMPD__)
+#define ST_RAMPD(M) ST_SFR (RAMPD,5,M)
+#define OP_RAMPD OP_SFR (RAMPD)
+#else
+#define ST_RAMPD(M) /* empty */
+#define OP_RAMPD /* empty */
+#endif
+
+/* Macros for all GPRs */
+#if defined __AVR_TINY__
+#define ST_REGS_LO(M) /* empty */
+#else
+#define ST_REGS_LO(M) \
+ ST(0,M) ST(1,M) ST(2,M) ST(3,M) \
+ ST(4,M) ST(5,M) ST(6,M) ST(7,M) \
+ ST(8,M) ST(9,M) ST(10,M) ST(11,M) \
+ ST(12,M) ST(13,M) ST(14,M) ST(15,M)
+#endif /* AVR_TINY */
+
+#define ST_REGS_HI(M) \
+ ST(16,M) ST(17,M) ST(18,M) ST(19,M) \
+ ST(20,M) ST(21,M) ST(22,M) ST(23,M) \
+ ST(24,M) ST(25,M) ST(26,M) ST(27,M) \
+ ST(28,M) ST(29,M) ST(30,M) ST(31,M)
+
+__attribute__((unused,naked,noinline,noclone))
+static void host_store1 (void)
+{
+ __asm __volatile__
+ ("nop"
+ CR ".global do_stores_before"
+ CR ".type do_stores_before,@function"
+ CR "do_stores_before:"
+ /* Funny values to some SFRs */
+ CR "ldi r31, 1 + 'Z'"
+ XX_RAMPZ
+ XX_RAMPY
+ XX_RAMPX
+ CR "dec __zero_reg__"
+ CR "clr r31"
+ XX_SREG
+ /* Must set I-flag due to RETI of ISR */
+ CR "sei"
+ /* Store core regs before ISR */
+ ST_RAMPX (mem1)
+ ST_RAMPY (mem1)
+ ST_RAMPZ (mem1)
+ ST_RAMPD (mem1)
+ ST_EIND (mem1)
+ ST_SREG (mem1)
+ CR "ldi r31, 0xaa"
+ CR "mov __tmp_reg__, r31"
+ CR "ldi r31, 31"
+ ST_REGS_LO (mem1)
+ ST_REGS_HI (mem1)
+ CR "ret"
+ : /* No outputs */
+ : [mem1] "i" (®info1), [first] "n" (FIRST_REG)
+ OP_RAMPX
+ OP_RAMPY
+ OP_RAMPZ
+ OP_RAMPD
+ OP_EIND
+ OP_SREG
+ : "memory", "r31");
+}
+
+__attribute__((unused,naked,noinline,noclone))
+static void host_store2 (void)
+{
+ __asm __volatile__
+ ("nop"
+ CR ".global do_stores_after"
+ CR ".type do_stores_after,@function"
+ CR "do_stores_after:"
+ /* Store core regs after ISR */
+ ST_REGS_LO (mem2)
+ ST_REGS_HI (mem2)
+ ST_RAMPX (mem2)
+ ST_RAMPY (mem2)
+ ST_RAMPZ (mem2)
+ ST_RAMPD (mem2)
+ ST_EIND (mem2)
+ ST_SREG (mem2)
+ /* Undo funny values */
+ CR "clr __zero_reg__"
+ OO_RAMPX
+ OO_RAMPY
+ OO_RAMPZ
+ CR "ret"
+ : /* No outputs */
+ : [mem2] "i" (®info2), [first] "n" (FIRST_REG)
+ OP_RAMPX
+ OP_RAMPY
+ OP_RAMPZ
+ OP_RAMPD
+ OP_EIND
+ OP_SREG
+ : "memory");
+}
+
+#define MK_CALL_ISR(vecno) \
+ __asm __volatile__ \
+ (/* Funny values to some SFRs */ \
+ /* Must set I-flag due to RETI of ISR */ \
+ /* Store core regs before ISR */ \
+ CR "%~call do_stores_before" \
+ /* Execute ISR */ \
+ CR "%~call __vectors + %[vect]" \
+ /* Store core regs after ISR */ \
+ /* Undo funny values */ \
+ CR "%~call do_stores_after" \
+ : /* No outputs */ \
+ : [vect] "i" (VEC_SIZE * (vecno)) \
+ , "i" (host_store1) \
+ , "i" (host_store2) \
+ : "memory", "r31")
+
+
+#define MK_RUN_ISR(N, IGMSK) \
+ \
+__attribute__((noinline,noclone)) \
+void run_isr_ ## N (void) \
+{ \
+ clear_reginfo(); \
+ MK_CALL_ISR (N); \
+ compare_reginfo (IGMSK); \
+}
+
+#endif /* ISR_TEST_H */
+
Index: gcc/testsuite/gcc.target/avr/torture/isr-01-simple.c
===================================================================
--- gcc/testsuite/gcc.target/avr/torture/isr-01-simple.c (nonexistent)
+++ gcc/testsuite/gcc.target/avr/torture/isr-01-simple.c (revision 250576)
@@ -0,0 +1,98 @@
+/* { dg-do run } */
+/* { dg-options "-std=c99" } */
+
+#include "../isr-test.h"
+
+int volatile v;
+
+/**********************************************************************/
+
+ISR (1, signal)
+{
+}
+
+MK_RUN_ISR (1, 0)
+
+void test1 (void)
+{
+ run_isr_1();
+}
+
+/**********************************************************************/
+
+ISR (2, signal)
+{
+ v++;
+}
+
+MK_RUN_ISR (2, 0)
+
+void test2 (void)
+{
+ v = 0;
+ run_isr_2();
+ if (v != 1)
+ __builtin_abort();
+}
+
+
+/**********************************************************************/
+
+ISR (3, signal)
+{
+ __asm __volatile__ ("$ lds r27, v"
+ "$ swap r27"
+ "$ sts v, r27"
+ ::: "memory", "r27");
+}
+
+MK_RUN_ISR (3, 0)
+
+void test3 (void)
+{
+ run_isr_3();
+ if (v != 0x10)
+ __builtin_abort();
+}
+
+/**********************************************************************/
+
+ISR (4, signal)
+{
+ __asm __volatile__ ("sts v,__zero_reg__" ::: "memory");
+}
+
+MK_RUN_ISR (4, 0)
+
+void test4 (void)
+{
+ run_isr_4();
+ if (v != 0)
+ __builtin_abort();
+}
+
+/**********************************************************************/
+
+ISR (5, signal)
+{
+ __asm __volatile__ ("clt");
+}
+
+MK_RUN_ISR (5, 0)
+
+void test5 (void)
+{
+ run_isr_5();
+}
+
+/**********************************************************************/
+
+int main (void)
+{
+ test1();
+ test2();
+ test3();
+ test4();
+ test5();
+ return 0;
+}
Index: gcc/testsuite/gcc.target/avr/torture/isr-02-call.c
===================================================================
--- gcc/testsuite/gcc.target/avr/torture/isr-02-call.c (nonexistent)
+++ gcc/testsuite/gcc.target/avr/torture/isr-02-call.c (revision 250576)
@@ -0,0 +1,60 @@
+/* { dg-do run } */
+/* { dg-options "-std=c99" } */
+
+#include "../isr-test.h"
+
+int volatile v;
+
+__attribute__((noinline,noclone))
+void inc_v (void)
+{
+ v++;
+}
+
+/**********************************************************************/
+
+ISR (1, signal)
+{
+ inc_v();
+}
+
+MK_RUN_ISR (1, 0)
+
+void test1 (void)
+{
+ run_isr_1();
+ if (v != 1)
+ __builtin_abort();
+}
+
+/**********************************************************************/
+
+ISR (2, signal)
+{
+ if (v == 1)
+ inc_v();
+ else
+ v += 2;
+}
+
+MK_RUN_ISR (2, 0)
+
+void test2 (void)
+{
+ run_isr_2();
+ if (v != 2)
+ __builtin_abort();
+ run_isr_2();
+ if (v != 4)
+ __builtin_abort();
+}
+
+
+/**********************************************************************/
+
+int main (void)
+{
+ test1();
+ test2();
+ return 0;
+}
Index: gcc/testsuite/gcc.target/avr/torture/isr-03-fixed.c
===================================================================
--- gcc/testsuite/gcc.target/avr/torture/isr-03-fixed.c (nonexistent)
+++ gcc/testsuite/gcc.target/avr/torture/isr-03-fixed.c (revision 250576)
@@ -0,0 +1,146 @@
+/* { dg-do run } */
+/* { dg-options "-std=gnu99 -fno-lto -fno-toplevel-reorder" } */
+
+// No LTO for now due to PR lto/68384.
+
+#ifdef __AVR_TINY__
+unsigned char reg2;
+#else
+register unsigned char reg2 __asm("r2");
+#endif
+
+#include "../isr-test.h"
+
+#define SET_REG(reg,val) \
+ do { \
+ reg = (val); \
+ __asm __volatile__("" : "+r" (reg)); \
+ } while (0) \
+
+#define GET_REG(reg) \
+ ({ \
+ __asm __volatile__("" : "+r" (reg)); \
+ reg; \
+ })
+
+/**********************************************************************/
+
+ISR (1, signal)
+{
+ reg2++;
+}
+
+MK_RUN_ISR (1, 1ul << 2)
+
+void test1 (void)
+{
+ SET_REG (reg2, 0);
+ run_isr_1();
+ if (GET_REG (reg2) != 1)
+ __builtin_abort();
+}
+
+/**********************************************************************/
+
+__attribute__((noinline,noclone))
+void inc_r2 (void)
+{
+ reg2++;
+}
+
+ISR (2, signal)
+{
+ inc_r2 ();
+}
+
+MK_RUN_ISR (2, 1ul << 2)
+
+void test2 (void)
+{
+ run_isr_2();
+ if (GET_REG (reg2) != 2)
+ __builtin_abort();
+}
+
+
+/**********************************************************************/
+
+ISR (3, signal)
+{
+#ifndef __AVR_TINY__
+ register char r4 __asm ("r4");
+ __asm __volatile ("inc %0" : "+r" (r4));
+ __asm __volatile ("inc r5" ::: "r5");
+#endif
+}
+
+MK_RUN_ISR (3, 0)
+
+void test3 (void)
+{
+ run_isr_3();
+}
+
+
+/**********************************************************************/
+
+#define CLOBB(reg) \
+ do { \
+ __asm __volatile__ ("inc " #reg ::: #reg); \
+ } while (0)
+
+ISR (4, signal)
+{
+ char volatile v;
+ v = 1;
+
+#ifndef __AVR_TINY__
+ CLOBB (r3);
+ CLOBB (r4);
+ CLOBB (r5);
+ CLOBB (r6);
+ CLOBB (r7);
+ CLOBB (r8);
+ CLOBB (r9);
+ CLOBB (r10);
+ CLOBB (r11);
+ CLOBB (r12);
+ CLOBB (r13);
+ CLOBB (r14);
+ CLOBB (r15);
+ CLOBB (r16);
+ CLOBB (r17);
+#endif
+
+ CLOBB (r18);
+ CLOBB (r19);
+ CLOBB (r20);
+ CLOBB (r21);
+ CLOBB (r22);
+ CLOBB (r23);
+ CLOBB (r24);
+ CLOBB (r25);
+ CLOBB (r26);
+ CLOBB (r27);
+ CLOBB (r30);
+ CLOBB (r31);
+}
+
+MK_RUN_ISR (4, 0)
+
+void test4 (void)
+{
+ run_isr_4();
+}
+
+
+/**********************************************************************/
+
+int main (void)
+{
+ test1();
+ test2();
+ test3();
+ test4();
+ return 0;
+}
Index: gcc/config/avr/avr.c
===================================================================
--- gcc/config/avr/avr.c (revision 250575)
+++ gcc/config/avr/avr.c (revision 250576)
@@ -3490,7 +3490,7 @@ out_movqi_r_mr (rtx_insn *insn, rtx op[]
if (CONSTANT_ADDRESS_P (x))
{
int n_words = AVR_TINY ? 1 : 2;
- return optimize > 0 && io_address_operand (x, QImode)
+ return io_address_operand (x, QImode)
? avr_asm_len ("in %0,%i1", op, plen, -1)
: avr_asm_len ("lds %0,%m1", op, plen, -n_words);
}
@@ -3745,7 +3745,7 @@ out_movhi_r_mr (rtx_insn *insn, rtx op[]
else if (CONSTANT_ADDRESS_P (base))
{
int n_words = AVR_TINY ? 2 : 4;
- return optimize > 0 && io_address_operand (base, HImode)
+ return io_address_operand (base, HImode)
? avr_asm_len ("in %A0,%i1" CR_TAB
"in %B0,%i1+1", op, plen, -2)
@@ -4873,7 +4873,7 @@ out_movqi_mr_r (rtx_insn *insn, rtx op[]
if (CONSTANT_ADDRESS_P (x))
{
int n_words = AVR_TINY ? 1 : 2;
- return optimize > 0 && io_address_operand (x, QImode)
+ return io_address_operand (x, QImode)
? avr_asm_len ("out %i0,%1", op, plen, -1)
: avr_asm_len ("sts %m0,%1", op, plen, -n_words);
}
@@ -4949,13 +4949,12 @@ avr_out_movhi_mr_r_xmega (rtx_insn *insn
if (CONSTANT_ADDRESS_P (base))
{
- int n_words = AVR_TINY ? 2 : 4;
- return optimize > 0 && io_address_operand (base, HImode)
+ return io_address_operand (base, HImode)
? avr_asm_len ("out %i0,%A1" CR_TAB
"out %i0+1,%B1", op, plen, -2)
: avr_asm_len ("sts %m0,%A1" CR_TAB
- "sts %m0+1,%B1", op, plen, -n_words);
+ "sts %m0+1,%B1", op, plen, -4);
}
if (reg_base > 0)
@@ -5132,7 +5131,7 @@ out_movhi_mr_r (rtx_insn *insn, rtx op[]
if (CONSTANT_ADDRESS_P (base))
{
int n_words = AVR_TINY ? 2 : 4;
- return optimize > 0 && io_address_operand (base, HImode)
+ return io_address_operand (base, HImode)
? avr_asm_len ("out %i0+1,%B1" CR_TAB
"out %i0,%A1", op, plen, -2)
@@ -10814,8 +10813,7 @@ avr_address_cost (rtx x, machine_mode mo
}
else if (CONSTANT_ADDRESS_P (x))
{
- if (optimize > 0
- && io_address_operand (x, QImode))
+ if (io_address_operand (x, QImode))
cost = 2;
}
Index: gcc/doc/invoke.texi
===================================================================
--- gcc/doc/invoke.texi (revision 250576)
+++ gcc/doc/invoke.texi (revision 250577)
@@ -637,7 +637,8 @@ -remap -trigraphs -undef -U@var{macro}
@emph{AVR Options}
@gccoptlist{-mmcu=@var{mcu} -maccumulate-args -mbranch-cost=@var{cost} @gol
-mcall-prologues -mint8 -mn_flash=@var{size} -mno-interrupts @gol
--mrelax -mrmw -mstrict-X -mtiny-stack -nodevicelib -Waddr-space-convert}
+-mrelax -mrmw -mstrict-X -mtiny-stack -nodevicelib -Waddr-space-convert @gol
+-Wmisspelled-isr}
@emph{Blackfin Options}
@gccoptlist{-mcpu=@var{cpu}@r{[}-@var{sirevision}@r{]} @gol
@@ -14449,12 +14450,17 @@ Only change the lower 8@tie{}bits of the
@item -nodevicelib
@opindex nodevicelib
-Don't link against AVR-LibC's device specific library @code{libdev.a}.
+Don't link against AVR-LibC's device specific library @code{lib<mcu>.a}.
@item -Waddr-space-convert
@opindex Waddr-space-convert
Warn about conversions between address spaces in the case where the
resulting address space is not contained in the incoming address space.
+
+@item -Wmisspelled-isr
+@opindex Wmisspelled-isr
+Warn if the ISR is misspelled, i.e. without @code{__vector} prefix.
+Enabled by default.
@end table
@subsubsection @code{EIND} and Devices with More Than 128 Ki Bytes of Flash
Index: gcc/config/avr/avr.opt
===================================================================
--- gcc/config/avr/avr.opt (revision 250576)
+++ gcc/config/avr/avr.opt (revision 250577)
@@ -91,6 +91,10 @@ Waddr-space-convert
Warning C Report Var(avr_warn_addr_space_convert) Init(0)
Warn if the address space of an address is changed.
+Wmisspelled-isr
+Warning C C++ Report Var(avr_warn_misspelled_isr) Init(1)
+Warn if the ISR is misspelled, i.e. without __vector prefix. Enabled by default.
+
mfract-convert-truncate
Target Report Mask(FRACT_CONV_TRUNC)
Allow to use truncation instead of rounding towards 0 for fractional int types.
Index: gcc/config/avr/avr.c
===================================================================
--- gcc/config/avr/avr.c (revision 250576)
+++ gcc/config/avr/avr.c (revision 250577)
@@ -735,12 +735,6 @@ avr_set_current_function (tree decl)
name = default_strip_name_encoding (name);
- /* Silently ignore 'signal' if 'interrupt' is present. AVR-LibC startet
- using this when it switched from SIGNAL and INTERRUPT to ISR. */
-
- if (cfun->machine->is_interrupt)
- cfun->machine->is_signal = 0;
-
/* Interrupt handlers must be void __vector (void) functions. */
if (args && TREE_CODE (TREE_VALUE (args)) != VOID_TYPE)
@@ -749,14 +743,36 @@ avr_set_current_function (tree decl)
if (TREE_CODE (ret) != VOID_TYPE)
error_at (loc, "%qs function cannot return a value", isr);
+#if defined WITH_AVRLIBC
+ /* Silently ignore 'signal' if 'interrupt' is present. AVR-LibC startet
+ using this when it switched from SIGNAL and INTERRUPT to ISR. */
+
+ if (cfun->machine->is_interrupt)
+ cfun->machine->is_signal = 0;
+
/* If the function has the 'signal' or 'interrupt' attribute, ensure
that the name of the function is "__vector_NN" so as to catch
when the user misspells the vector name. */
if (!STR_PREFIX_P (name, "__vector"))
- warning_at (loc, 0, "%qs appears to be a misspelled %s handler",
- name, isr);
+ warning_at (loc, OPT_Wmisspelled_isr, "%qs appears to be a misspelled "
+ "%qs handler, missing %<__vector%> prefix", name, isr);
+#endif // AVR-LibC naming conventions
+ }
+
+#if defined WITH_AVRLIBC
+ // Common problem is using "ISR" without first including avr/interrupt.h.
+ const char *name = IDENTIFIER_POINTER (DECL_NAME (decl));
+ name = default_strip_name_encoding (name);
+ if (0 == strcmp ("ISR", name)
+ || 0 == strcmp ("INTERRUPT", name)
+ || 0 == strcmp ("SIGNAL", name))
+ {
+ warning_at (loc, OPT_Wmisspelled_isr, "%qs is a reserved indentifier"
+ " in AVR-LibC. Consider %<#include <avr/interrupt.h>%>"
+ " before using the %qs macro", name, name);
}
+#endif // AVR-LibC naming conventions
/* Don't print the above diagnostics more than once. */