[AArch64, Patch] Generate MLA when multiply + add vector by scalar

[Jackson Woodruff <jackson dot woodruff at foss dot arm dot com>]

Hi all,

This merges vector multiplies and adds into a single mla instruction 
when the multiplication is done by a scalar.

Currently, for the following:

    typedef int __attribute__((vector_size(16))) vec;

    vec
    mla0(vec v0, vec v1, vec v2)
    {
      return v0 + v1 * v2[0];
    }

    vec
    mla1(vec v0, vec v1, int v2)
    {
      return v0 + v1 * c;
    }

The function `mla0` outputs a multiply accumulate by element 
instruction. `mla1` outputs two vector operations (multiply followed by 
add). That is, we currently have:

    mla0:
        mla    v0.4s, v1.4s, v2.s[0]
        ret

    mla1:
        fmov   s2, w0
        mul    v1.4s, v1.4s, v2.s[0]
        add    v0.4s, v1.4s, v0.4s
        ret

This patch replaces this with something similar to `mla0`:

    mla1:
        fmov   s2, w0
        mla    v0.4s, v1.4s, v2.s[0]

This is also done for the identical case for a multiply followed by a 
subtract of vectors with an integer operand on the multiply. Also add 
testcases for this.

Bootstrap and testsuite run on aarch64. OK for trunk?

Jackson

Changelog entry:

gcc/

2017-06-06  Jackson Woodruff <jackson.woodruff@arm.com>

	* config/aarch64/aarch64-simd.md (aarch64_mla_elt_merge<mode>,

	aarch64_mls_elt_merge<mode>, aarch64_fma4_elt_merge<mode>,

	aarch64_fnma_elt_merge<mode>): New define_insns to generate

	multiply accumulate instructions for unmerged

	multiply add vector instructions.


gcc/testsuite/

2017-06-06  Jackson Woodruff <jackson.woodruff@arm.com>

	* gcc.target/aarch64/simd/vmla_elem_1.c: New.

Attachment: patchfile
Description: Text document