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Re: [PATCH, VAX] Correct ffs instruction constraint
- From: Jeff Law <law at redhat dot com>
- To: coypu at sdf dot org, gcc-patches at gcc dot gnu dot org
- Cc: matt at 3am-software dot com
- Date: Thu, 29 Jun 2017 13:44:55 -0600
- Subject: Re: [PATCH, VAX] Correct ffs instruction constraint
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On 06/29/2017 09:47 AM, firstname.lastname@example.org wrote:
> On Tue, Jun 20, 2017 at 08:05:42PM +0000, email@example.com wrote:
>> VAX' FFS as variable-length bit field instruction uses a "base"
>> operand of type "vb" meaning "byte address".
>> "base" can be 32 bits (SI) and due to the definition of
>> ffssi2/__builtin_ffs() with the operand constraint "m", code can be
>> emitted which incorrectly implies a mode-dependent (= longword, for
>> the 32-bit operand) address.
>> File scsipi_base.c compiled with -Os for our VAX install kernel shows:
>> ffs $0x0,$0x20,0x50(r11)[r0],r9
>> Apparently, 0x50(r11)[r0] as a longword address is assumed to be
>> evaluated in longword context by FFS, but the instruction expects a
>> byte address.
>> Our fix is to change the operand constraint from "m" to "Q", i. e.
>> "operand is a MEM that does not have a mode-dependent address", which
>> results in:
>> moval 0x50(r11)[r0],r1
>> ffs $0x0,$0x20,(r1),r9
>> MOVAL evaluates the source operand/address in longword context, so
>> effectively converts the word address to a byte address for FFS.
>> See NetBSD PR port-vax/51761 (http://gnats.netbsd.org/51761) and
>> discussion on port-vax mailing list
>> 2017-06-20 Maya Rashish <firstname.lastname@example.org>
>> * gcc/config/vax/builtins.md: Correct ffssi2_internal
>> instruction constraint.
Ideally we'd like to have a testcase for this in the regression suite.
If you could provide the .i file and options used which generated the
incorrect ffs instruction I can use the reduction tools with a cross
compiler to produce a nice simple test for the testsuite.