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Re: [PATCH, ARM] Implement __ARM_FEATURE_COPROC coprocessor intrinsic feature macro


Hi Christophe,

On 21/06/17 17:57, Christophe Lyon wrote:
Hi,


On 19 June 2017 at 11:32, Richard Earnshaw (lists)
<Richard.Earnshaw@arm.com> wrote:
On 16/06/17 15:56, Prakhar Bahuguna wrote:
On 16/06/2017 15:37:18, Richard Earnshaw (lists) wrote:
On 16/06/17 08:48, Prakhar Bahuguna wrote:
On 15/06/2017 17:23:43, Richard Earnshaw (lists) wrote:
On 14/06/17 10:35, Prakhar Bahuguna wrote:
The ARM ACLE defines the __ARM_FEATURE_COPROC macro which indicates which
coprocessor intrinsics are available for the target. If __ARM_FEATURE_COPROC is
undefined, the target does not support coprocessor intrinsics. The feature
levels are defined as follows:

+---------+-----------+--------------------------------------------------+
| **Bit** | **Value** | **Intrinsics Available**                         |
+---------+-----------+--------------------------------------------------+
| 0       | 0x1       | __arm_cdp __arm_ldc, __arm_ldcl, __arm_stc,      |
|         |           | __arm_stcl, __arm_mcr and __arm_mrc              |
+---------+-----------+--------------------------------------------------+
| 1       | 0x2       | __arm_cdp2, __arm_ldc2, __arm_stc2, __arm_ldc2l, |
|         |           | __arm_stc2l, __arm_mcr2 and __arm_mrc2           |
+---------+-----------+--------------------------------------------------+
| 2       | 0x4       | __arm_mcrr and __arm_mrrc                        |
+---------+-----------+--------------------------------------------------+
| 3       | 0x8       | __arm_mcrr2 and __arm_mrrc2                      |
+---------+-----------+--------------------------------------------------+

This patch implements full support for this feature macro as defined in section
5.9 of the ACLE
(https://developer.arm.com/products/software-development-tools/compilers/arm-compiler-5/docs/101028/latest/5-feature-test-macros).

gcc/ChangeLog:

2017-06-14  Prakhar Bahuguna  <prakhar.bahuguna@arm.com>

   * config/arm/arm-c.c (arm_cpu_builtins): New block to define
    __ARM_FEATURE_COPROC according to support.

2017-06-14  Prakhar Bahuguna  <prakhar.bahuguna@arm.com>
   * gcc/testsuite/gcc.target/arm/acle/cdp.c: Add feature macro bitmap
   test.
   * gcc/testsuite/gcc.target/arm/acle/cdp2.c: Likewise.
   * gcc/testsuite/gcc.target/arm/acle/ldc.c: Likewise.
   * gcc/testsuite/gcc.target/arm/acle/ldc2.c: Likewise.
   * gcc/testsuite/gcc.target/arm/acle/ldc2l.c: Likewise.
   * gcc/testsuite/gcc.target/arm/acle/ldcl.c: Likewise.
   * gcc/testsuite/gcc.target/arm/acle/mcr.c: Likewise.
   * gcc/testsuite/gcc.target/arm/acle/mcr2.c: Likewise.
   * gcc/testsuite/gcc.target/arm/acle/mcrr.c: Likewise.
   * gcc/testsuite/gcc.target/arm/acle/mcrr2.c: Likewise.
   * gcc/testsuite/gcc.target/arm/acle/mrc.c: Likewise.
   * gcc/testsuite/gcc.target/arm/acle/mrc2.c: Likewise.
   * gcc/testsuite/gcc.target/arm/acle/mrrc.c: Likewise.
   * gcc/testsuite/gcc.target/arm/acle/mrrc2.c: Likewise.
   * gcc/testsuite/gcc.target/arm/acle/stc.c: Likewise.
   * gcc/testsuite/gcc.target/arm/acle/stc2.c: Likewise.
   * gcc/testsuite/gcc.target/arm/acle/stc2l.c: Likewise.
   * gcc/testsuite/gcc.target/arm/acle/stcl.c: Likewise.

Testing done: ACLE regression tests updated with tests for feature macro bits.
All regression tests pass.

Okay for trunk?


0001-Implement-__ARM_FEATURE_COPROC-coprocessor-intrinsic.patch


 From 79d71aec9d2bdee936b240ae49368ff5f8d8fc48 Mon Sep 17 00:00:00 2001
From: Prakhar Bahuguna <prakhar.bahuguna@arm.com>
Date: Tue, 2 May 2017 13:43:40 +0100
Subject: [PATCH] Implement __ARM_FEATURE_COPROC coprocessor intrinsic feature
  macro

---
  gcc/config/arm/arm-c.c                    | 19 +++++++++++++++++++
  gcc/testsuite/gcc.target/arm/acle/cdp.c   |  3 +++
  gcc/testsuite/gcc.target/arm/acle/cdp2.c  |  3 +++
  gcc/testsuite/gcc.target/arm/acle/ldc.c   |  3 +++
  gcc/testsuite/gcc.target/arm/acle/ldc2.c  |  3 +++
  gcc/testsuite/gcc.target/arm/acle/ldc2l.c |  3 +++
  gcc/testsuite/gcc.target/arm/acle/ldcl.c  |  3 +++
  gcc/testsuite/gcc.target/arm/acle/mcr.c   |  3 +++
  gcc/testsuite/gcc.target/arm/acle/mcr2.c  |  3 +++
  gcc/testsuite/gcc.target/arm/acle/mcrr.c  |  3 +++
  gcc/testsuite/gcc.target/arm/acle/mcrr2.c |  3 +++
  gcc/testsuite/gcc.target/arm/acle/mrc.c   |  3 +++
  gcc/testsuite/gcc.target/arm/acle/mrc2.c  |  3 +++
  gcc/testsuite/gcc.target/arm/acle/mrrc.c  |  3 +++
  gcc/testsuite/gcc.target/arm/acle/mrrc2.c |  3 +++
  gcc/testsuite/gcc.target/arm/acle/stc.c   |  3 +++
  gcc/testsuite/gcc.target/arm/acle/stc2.c  |  3 +++
  gcc/testsuite/gcc.target/arm/acle/stc2l.c |  3 +++
  gcc/testsuite/gcc.target/arm/acle/stcl.c  |  3 +++
  19 files changed, 73 insertions(+)

diff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c
index 3abe7d1f1f5..3daf4e5e1f3 100644
--- a/gcc/config/arm/arm-c.c
+++ b/gcc/config/arm/arm-c.c
@@ -200,6 +200,25 @@ arm_cpu_builtins (struct cpp_reader* pfile)
    def_or_undef_macro (pfile, "__ARM_FEATURE_IDIV", TARGET_IDIV);

    def_or_undef_macro (pfile, "__ARM_ASM_SYNTAX_UNIFIED__", inline_asm_unified);
+
+  if ((!TARGET_THUMB || TARGET_THUMB2) && arm_arch4 &&

(!TARGET_THUMB || TARGET_THUMB2) looks to me to be equivalent to
TARGET_32BIT.  That should be used in preference.
TARGET_32BIT is defined to be (TARGET_ARM || arm_arch_thumb2). This is not true
for ARMv8-M Baseline which supports neither ARM mode nor the full Thumb2 mode,
so this alternative is used.

That's irrelevant since that case is caught by the arm_arch_notm test.

#define TARGET_32BIT                    (TARGET_ARM || arm_arch_thumb2)
#define TARGET_THUMB2                   (TARGET_THUMB && arm_arch_thumb2)
#define TARGET_ARM                      (! TARGET_THUMB)

So (!TARGET_THUMB || TARGET_THUMB2)
  = (!TARGET_THUMB || (TARGET_THUMB && arm_arch_thumb2))
   = ((!TARGET_THUMB || TARGET_THUMB) && (!TARGET_THUMB || arm_arch_thumb2))
    = (1 && (!TARGET_THUMB || arm_arch_thumb2))
     = (!TARGET_THUMB || arm_arch_thumb2)
      = (TARGET_ARM || arm_arch_thumb2)
       = TARGET_32BIT

Please use the latter.

The same conditional is used by arm_acle.h.

A patch to fix that is pre-approved.



Why the test for arm_arch4?  Co-processor instructions in ARM state go
back to the dawn of time.
In arm_acle.h, the coprocessor intrinsics are only enabled for ARMv4 and above,
hence the macro is only available when the intrinsics are available.

GNU coding style requires operators on multi-line statements to be at
the start of the continuation lines, not at the end of lines.

+      !(arm_arch8 && arm_arch_notm))
+    {
+      int coproc_level = 0x1;
+
+      if (arm_arch5)
+ coproc_level |= 0x2;
+      if (arm_arch5e)
+ coproc_level |= 0x4;
+      if (arm_arch6)
+ coproc_level |= 0x8;
+
+      builtin_define_with_int_value ("__ARM_FEATURE_COPROC", coproc_level);
+    }
+  else
+    {
+      cpp_undef (pfile, "__ARM_FEATURE_COPROC");
+    }

Redundant braces around single statement.

R.

Thanks, will fix these.



Updated to use TARGET_32BIT.


OK.

R.


0001-Implement-__ARM_FEATURE_COPROC-coprocessor-intrinsic.patch


 From 2ebd3971c9fabab8afe3e516dc9fa0bebd55bf3e Mon Sep 17 00:00:00 2001
From: Prakhar Bahuguna <prakhar.bahuguna@arm.com>
Date: Tue, 2 May 2017 13:43:40 +0100
Subject: [PATCH] Implement __ARM_FEATURE_COPROC coprocessor intrinsic feature
  macro

---
  gcc/config/arm/arm-c.c                    | 16 ++++++++++++++++
  gcc/testsuite/gcc.target/arm/acle/cdp.c   |  3 +++
  gcc/testsuite/gcc.target/arm/acle/cdp2.c  |  3 +++
  gcc/testsuite/gcc.target/arm/acle/ldc.c   |  3 +++
  gcc/testsuite/gcc.target/arm/acle/ldc2.c  |  3 +++
  gcc/testsuite/gcc.target/arm/acle/ldc2l.c |  3 +++
  gcc/testsuite/gcc.target/arm/acle/ldcl.c  |  3 +++
  gcc/testsuite/gcc.target/arm/acle/mcr.c   |  3 +++
  gcc/testsuite/gcc.target/arm/acle/mcr2.c  |  3 +++
  gcc/testsuite/gcc.target/arm/acle/mcrr.c  |  3 +++
  gcc/testsuite/gcc.target/arm/acle/mcrr2.c |  3 +++
  gcc/testsuite/gcc.target/arm/acle/mrc.c   |  3 +++
  gcc/testsuite/gcc.target/arm/acle/mrc2.c  |  3 +++
  gcc/testsuite/gcc.target/arm/acle/mrrc.c  |  3 +++
  gcc/testsuite/gcc.target/arm/acle/mrrc2.c |  3 +++
  gcc/testsuite/gcc.target/arm/acle/stc.c   |  3 +++
  gcc/testsuite/gcc.target/arm/acle/stc2.c  |  3 +++
  gcc/testsuite/gcc.target/arm/acle/stc2l.c |  3 +++
  gcc/testsuite/gcc.target/arm/acle/stcl.c  |  3 +++
  19 files changed, 70 insertions(+)

diff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c
index 3abe7d1f1f5..a3daa3220a2 100644
--- a/gcc/config/arm/arm-c.c
+++ b/gcc/config/arm/arm-c.c
@@ -200,6 +200,22 @@ arm_cpu_builtins (struct cpp_reader* pfile)
    def_or_undef_macro (pfile, "__ARM_FEATURE_IDIV", TARGET_IDIV);

    def_or_undef_macro (pfile, "__ARM_ASM_SYNTAX_UNIFIED__", inline_asm_unified);
+
+  if (TARGET_32BIT && arm_arch4 && !(arm_arch8 && arm_arch_notm))

I think the condition is wrong: if one uses -march=armv8-a, the
modified testcases fail with
__ARM_FEATURE_COPROC does not have correct feature bits set

The attached patch changes the above condition into:
+  if (TARGET_32BIT && arm_arch4 && !(arm_arch8 && !arm_arch_notm))
(which is not very readable with all the negations....)

That seems wrong. ARMv8-A was intended, not ARMv8-R. However the tests should be fixed for the macro not to be tested on ARMv8-A. I'll provide a fix to this effect.

Best regards,

Thomas


With this, the tests pass with -march=armv8-a (or when the compiler is
built --with-cpu=cortex-a57).

OK?

Thanks,

Christophe


+    {
+      int coproc_level = 0x1;
+
+      if (arm_arch5)
+     coproc_level |= 0x2;
+      if (arm_arch5e)
+     coproc_level |= 0x4;
+      if (arm_arch6)
+     coproc_level |= 0x8;
+
+      builtin_define_with_int_value ("__ARM_FEATURE_COPROC", coproc_level);
+    }
+  else
+      cpp_undef (pfile, "__ARM_FEATURE_COPROC");
  }

  void
diff --git a/gcc/testsuite/gcc.target/arm/acle/cdp.c b/gcc/testsuite/gcc.target/arm/acle/cdp.c
index 28b218e7cfc..cebd8c4024e 100644
--- a/gcc/testsuite/gcc.target/arm/acle/cdp.c
+++ b/gcc/testsuite/gcc.target/arm/acle/cdp.c
@@ -5,6 +5,9 @@
  /* { dg-require-effective-target arm_coproc1_ok } */

  #include "arm_acle.h"
+#if (__ARM_FEATURE_COPROC & 0x1) == 0
+  #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
+#endif

  void test_cdp (void)
  {
diff --git a/gcc/testsuite/gcc.target/arm/acle/cdp2.c b/gcc/testsuite/gcc.target/arm/acle/cdp2.c
index 00bcd502b56..945d435d2fb 100644
--- a/gcc/testsuite/gcc.target/arm/acle/cdp2.c
+++ b/gcc/testsuite/gcc.target/arm/acle/cdp2.c
@@ -5,6 +5,9 @@
  /* { dg-require-effective-target arm_coproc2_ok } */

  #include "arm_acle.h"
+#if (__ARM_FEATURE_COPROC & 0x2) == 0
+  #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
+#endif

  void test_cdp2 (void)
  {
diff --git a/gcc/testsuite/gcc.target/arm/acle/ldc.c b/gcc/testsuite/gcc.target/arm/acle/ldc.c
index f45f25d8c97..cd57343208f 100644
--- a/gcc/testsuite/gcc.target/arm/acle/ldc.c
+++ b/gcc/testsuite/gcc.target/arm/acle/ldc.c
@@ -5,6 +5,9 @@
  /* { dg-require-effective-target arm_coproc1_ok } */

  #include "arm_acle.h"
+#if (__ARM_FEATURE_COPROC & 0x1) == 0
+  #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
+#endif

  extern void * p;

diff --git a/gcc/testsuite/gcc.target/arm/acle/ldc2.c b/gcc/testsuite/gcc.target/arm/acle/ldc2.c
index 433bf8a1204..d7691e30d76 100644
--- a/gcc/testsuite/gcc.target/arm/acle/ldc2.c
+++ b/gcc/testsuite/gcc.target/arm/acle/ldc2.c
@@ -5,6 +5,9 @@
  /* { dg-require-effective-target arm_coproc2_ok } */

  #include "arm_acle.h"
+#if (__ARM_FEATURE_COPROC & 0x2) == 0
+  #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
+#endif

  extern void * p;

diff --git a/gcc/testsuite/gcc.target/arm/acle/ldc2l.c b/gcc/testsuite/gcc.target/arm/acle/ldc2l.c
index 88c8aa44765..9ee63afa055 100644
--- a/gcc/testsuite/gcc.target/arm/acle/ldc2l.c
+++ b/gcc/testsuite/gcc.target/arm/acle/ldc2l.c
@@ -5,6 +5,9 @@
  /* { dg-require-effective-target arm_coproc2_ok } */

  #include "arm_acle.h"
+#if (__ARM_FEATURE_COPROC & 0x2) == 0
+  #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
+#endif

  extern void * p;

diff --git a/gcc/testsuite/gcc.target/arm/acle/ldcl.c b/gcc/testsuite/gcc.target/arm/acle/ldcl.c
index 72a97f1d7b7..a6bfd9011dc 100644
--- a/gcc/testsuite/gcc.target/arm/acle/ldcl.c
+++ b/gcc/testsuite/gcc.target/arm/acle/ldcl.c
@@ -5,6 +5,9 @@
  /* { dg-require-effective-target arm_coproc1_ok } */

  #include "arm_acle.h"
+#if (__ARM_FEATURE_COPROC & 0x1) == 0
+  #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
+#endif

  extern void * p;

diff --git a/gcc/testsuite/gcc.target/arm/acle/mcr.c b/gcc/testsuite/gcc.target/arm/acle/mcr.c
index 93f977a2bdb..7095dcbc3ad 100644
--- a/gcc/testsuite/gcc.target/arm/acle/mcr.c
+++ b/gcc/testsuite/gcc.target/arm/acle/mcr.c
@@ -5,6 +5,9 @@
  /* { dg-require-effective-target arm_coproc1_ok } */

  #include "arm_acle.h"
+#if (__ARM_FEATURE_COPROC & 0x1) == 0
+  #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
+#endif

  void test_mcr (uint32_t a)
  {
diff --git a/gcc/testsuite/gcc.target/arm/acle/mcr2.c b/gcc/testsuite/gcc.target/arm/acle/mcr2.c
index 5b60d10ff25..2a4b0ce4559 100644
--- a/gcc/testsuite/gcc.target/arm/acle/mcr2.c
+++ b/gcc/testsuite/gcc.target/arm/acle/mcr2.c
@@ -5,6 +5,9 @@
  /* { dg-require-effective-target arm_coproc2_ok } */

  #include "arm_acle.h"
+#if (__ARM_FEATURE_COPROC & 0x2) == 0
+  #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
+#endif

  void test_mcr2 (uint32_t a)
  {
diff --git a/gcc/testsuite/gcc.target/arm/acle/mcrr.c b/gcc/testsuite/gcc.target/arm/acle/mcrr.c
index dcc223c713d..bcfbe1a4855 100644
--- a/gcc/testsuite/gcc.target/arm/acle/mcrr.c
+++ b/gcc/testsuite/gcc.target/arm/acle/mcrr.c
@@ -5,6 +5,9 @@
  /* { dg-require-effective-target arm_coproc3_ok } */

  #include "arm_acle.h"
+#if (__ARM_FEATURE_COPROC & 0x4) == 0
+  #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
+#endif

  void test_mcrr (uint64_t a)
  {
diff --git a/gcc/testsuite/gcc.target/arm/acle/mcrr2.c b/gcc/testsuite/gcc.target/arm/acle/mcrr2.c
index 10f2014d447..afd07e67f21 100644
--- a/gcc/testsuite/gcc.target/arm/acle/mcrr2.c
+++ b/gcc/testsuite/gcc.target/arm/acle/mcrr2.c
@@ -5,6 +5,9 @@
  /* { dg-require-effective-target arm_coproc4_ok } */

  #include "arm_acle.h"
+#if (__ARM_FEATURE_COPROC & 0x8) == 0
+  #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
+#endif

  void test_mcrr2 (uint64_t a)
  {
diff --git a/gcc/testsuite/gcc.target/arm/acle/mrc.c b/gcc/testsuite/gcc.target/arm/acle/mrc.c
index 34ca6a1638c..809b6c9c265 100644
--- a/gcc/testsuite/gcc.target/arm/acle/mrc.c
+++ b/gcc/testsuite/gcc.target/arm/acle/mrc.c
@@ -5,6 +5,9 @@
  /* { dg-require-effective-target arm_coproc1_ok } */

  #include "arm_acle.h"
+#if (__ARM_FEATURE_COPROC & 0x1) == 0
+  #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
+#endif

  uint32_t test_mrc (void)
  {
diff --git a/gcc/testsuite/gcc.target/arm/acle/mrc2.c b/gcc/testsuite/gcc.target/arm/acle/mrc2.c
index 3b72a402224..4c06ea39b37 100644
--- a/gcc/testsuite/gcc.target/arm/acle/mrc2.c
+++ b/gcc/testsuite/gcc.target/arm/acle/mrc2.c
@@ -5,6 +5,9 @@
  /* { dg-require-effective-target arm_coproc2_ok } */

  #include "arm_acle.h"
+#if (__ARM_FEATURE_COPROC & 0x2) == 0
+  #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
+#endif

  uint32_t test_mrc2 (void)
  {
diff --git a/gcc/testsuite/gcc.target/arm/acle/mrrc.c b/gcc/testsuite/gcc.target/arm/acle/mrrc.c
index 28c3b8ea6b5..802de083d5c 100644
--- a/gcc/testsuite/gcc.target/arm/acle/mrrc.c
+++ b/gcc/testsuite/gcc.target/arm/acle/mrrc.c
@@ -5,6 +5,9 @@
  /* { dg-require-effective-target arm_coproc3_ok } */

  #include "arm_acle.h"
+#if (__ARM_FEATURE_COPROC & 0x4) == 0
+  #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
+#endif

  uint64_t test_mrrc (void)
  {
diff --git a/gcc/testsuite/gcc.target/arm/acle/mrrc2.c b/gcc/testsuite/gcc.target/arm/acle/mrrc2.c
index 5b7aab06222..adf39563e29 100644
--- a/gcc/testsuite/gcc.target/arm/acle/mrrc2.c
+++ b/gcc/testsuite/gcc.target/arm/acle/mrrc2.c
@@ -5,6 +5,9 @@
  /* { dg-require-effective-target arm_coproc4_ok } */

  #include "arm_acle.h"
+#if (__ARM_FEATURE_COPROC & 0x8) == 0
+  #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
+#endif

  uint64_t test_mrrc2 (void)
  {
diff --git a/gcc/testsuite/gcc.target/arm/acle/stc.c b/gcc/testsuite/gcc.target/arm/acle/stc.c
index 7c6e04fe0fe..2714f65787e 100644
--- a/gcc/testsuite/gcc.target/arm/acle/stc.c
+++ b/gcc/testsuite/gcc.target/arm/acle/stc.c
@@ -5,6 +5,9 @@
  /* { dg-require-effective-target arm_coproc1_ok } */

  #include "arm_acle.h"
+#if (__ARM_FEATURE_COPROC & 0x1) == 0
+  #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
+#endif

  extern void * p;

diff --git a/gcc/testsuite/gcc.target/arm/acle/stc2.c b/gcc/testsuite/gcc.target/arm/acle/stc2.c
index 1578f7b1136..0a84652e0f0 100644
--- a/gcc/testsuite/gcc.target/arm/acle/stc2.c
+++ b/gcc/testsuite/gcc.target/arm/acle/stc2.c
@@ -5,6 +5,9 @@
  /* { dg-require-effective-target arm_coproc2_ok } */

  #include "arm_acle.h"
+#if (__ARM_FEATURE_COPROC & 0x2) == 0
+  #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
+#endif

  extern void * p;

diff --git a/gcc/testsuite/gcc.target/arm/acle/stc2l.c b/gcc/testsuite/gcc.target/arm/acle/stc2l.c
index 7adbd60d48a..2453d04ad72 100644
--- a/gcc/testsuite/gcc.target/arm/acle/stc2l.c
+++ b/gcc/testsuite/gcc.target/arm/acle/stc2l.c
@@ -5,6 +5,9 @@
  /* { dg-require-effective-target arm_coproc2_ok } */

  #include "arm_acle.h"
+#if (__ARM_FEATURE_COPROC & 0x2) == 0
+  #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
+#endif

  extern void * p;

diff --git a/gcc/testsuite/gcc.target/arm/acle/stcl.c b/gcc/testsuite/gcc.target/arm/acle/stcl.c
index 2fd5edd02d7..affdaa27982 100644
--- a/gcc/testsuite/gcc.target/arm/acle/stcl.c
+++ b/gcc/testsuite/gcc.target/arm/acle/stcl.c
@@ -5,6 +5,9 @@
  /* { dg-require-effective-target arm_coproc1_ok } */

  #include "arm_acle.h"
+#if (__ARM_FEATURE_COPROC & 0x1) == 0
+  #error "__ARM_FEATURE_COPROC does not have correct feature bits set"
+#endif

  extern void * p;





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